Abstract: A method of manufacturing a photo mask includes determining an enhancement region, in a simulation zone, of a layout pattern of a photo mask. The method includes determining a stitching mobility zone inside the simulation zone, determining an optimization mobility zone inside the stitching mobility zone, and performing an inverse lithographic transformation (ILT) operation of the layout pattern in the simulation zone to generate an ILT adjusted layout pattern in the simulation zone. The method includes combining a weighted sum of the ILT adjusted layout pattern and the layout pattern in the simulation zone to generate an enhanced layout pattern of the photo mask in the simulation zone using a first weighting function inside enhancement region, a second weighting function between boundaries of the enhancement region and the optimization mobility zone, and a third weighting function between boundaries of the optimization mobility zone and the stitching mobility zone.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

Abstract: A method of manufacturing a photo mask includes determining an enhancement region, in a simulation zone, of a layout pattern of a photo mask. The method includes determining a stitching mobility zone inside the simulation zone, determining an optimization mobility zone inside the stitching mobility zone, and performing an inverse lithographic transformation (ILT) operation of the layout pattern in the simulation zone to generate an ILT adjusted layout pattern in the simulation zone. The method includes combining a weighted sum of the ILT adjusted layout pattern and the layout pattern in the simulation zone to generate an enhanced layout pattern of the photo mask in the simulation zone using a first weighting function inside enhancement region, a second weighting function between boundaries of the enhancement region and the optimization mobility zone, and a third weighting function between boundaries of the optimization mobility zone and the stitching mobility zone.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: A method performed by a computing system includes receiving a layout pattern, receiving a target pattern associated with the layout pattern, receiving a set of constraints related to the target pattern, simulating a first contour associated with the layout pattern, determining a first difference between the first contour and the target pattern, simulating a second contour associated with a modified layout pattern, and determining a second difference between the second contour and a modified target pattern. The modified target pattern is different than the target pattern and within the constraints. The method further includes fabricating a mask having the final layout pattern.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.