Patents by Inventor Daniel Blanks

Daniel Blanks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SURFACE DECORATION DEVICE AND METHOD
    Publication number: 20240331582
    Abstract: A surface decoration device and method for decorating a surface with sports related indicia includes a tile including a top surface, a bottom surface, and a perimeter edge. A sports related indicia is positioned on the top surface of the tile and displays indicia corresponding to a sports team. A fastener is mounted to the tile and fastens the tile to a floor surface.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Inventor: Daniel Blanks
  • Graphical analysis of complex clock trees
    Patent number: 10255396
    Abstract: This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic connectivity presentation based on a conformance of the portion of the clock tree to timing constraints for the clock tree. The computing system can compress the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree. The compacted representation can retain a hierarchical connectivity of the other portions of the clock tree. The computing system can generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree coupled to at least one compacted representation of other portions of the clock tree.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 9, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Hamid Bouzouzou, Pierre-Olivier Ribet, Daniel Blanks, Patrick Richier, Laurent Masse-Navette
  • GRAPHICAL ANALYSIS OF COMPLEX CLOCK TREES
    Publication number: 20170293706
    Abstract: This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic connectivity presentation based on a conformance of the portion of the clock tree to timing constraints for the clock tree. The computing system can compress the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree. The compacted representation can retain a hierarchical connectivity of the other portions of the clock tree. The computing system can generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree coupled to at least one compacted representation of other portions of the clock tree.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 12, 2017
    Inventors: Hamid Bouzouzou, Pierre-Olivier Ribet, Daniel Blanks, Patrick Blanks, Laurent Masse-Navette