Patents by Inventor Daniel Borkowski
Daniel Borkowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220212951Abstract: Infiltration system management and operation is provided using leading indicators. These leading indicators may be sensed at various locations and compared to a target value or range or other criteria when making adjustments to blower, vacuum, pump, or valve operation of an infiltration system. Other operational components or parameters may also be adjusted when considering one or more leading indicator. For instance, sacrificial carbon sources may also be added or replaced based on the status of a leading indicator and its comparison to a target value or range.Type: ApplicationFiled: January 5, 2022Publication date: July 7, 2022Inventors: David A. Potts, Daniel Borkowski
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Patent number: 11059732Abstract: Reconfigurable water leaching modules are provided herein. These modules may comprise a plurality of dosing conduits and a plurality of leaching channels fluidly coupled to the dosing conduits where the leaching channels are reconfigurable from a first retracted position to a second extended position and where the leaching channels may hang downwardly from the dosing conduits in the second extended position.Type: GrantFiled: December 30, 2019Date of Patent: July 13, 2021Assignee: GEOMATRIX SYSTEMS, LLCInventors: David A. Potts, Daniel Borkowski, David Jewett, Michael Joseph Borruso
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Publication number: 20200131064Abstract: Reconfigurable water leaching modules are provided herein. These modules may comprise a plurality of dosing conduits and a plurality of leaching channels fluidly coupled to the dosing conduits where the leaching channels are reconfigurable from a first retracted position to a second extended position and where the leaching channels may hang downwardly from the dosing conduits in the second extended position.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Inventors: David A. Potts, Daniel Borkowski, David Jewett, Michael Joseph Borruso
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Patent number: 10550561Abstract: Wastewater leaching chambers and leaching channels are disclosed. The chambers may include a recess for receiving a wastewater supply, the recess serving to lower the overall height of the combined chamber and supply. The recess also configured to tightly seat the supply and form a gap therebetween. Leaching channels having a high aspect ratio may also be coupled to or otherwise in fluid communication with the chamber.Type: GrantFiled: August 15, 2017Date of Patent: February 4, 2020Assignee: GEOMATRIX SYSTEMS, LLCInventors: David A Potts, Daniel Borkowski, David Jewett
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Patent number: 10519053Abstract: Reconfigurable water leaching modules are provided herein. These modules may comprise a plurality of dosing conduits and a plurality of leaching channels fluidly coupled to the dosing conduits where the leaching channels are reconfigurable from a first retracted position to a second extended position and where the leaching channels may hang downwardly from the dosing conduits in the second extended position.Type: GrantFiled: April 26, 2018Date of Patent: December 31, 2019Assignee: GEOMATRIX SYSTEMS, LLCInventors: David A Potts, Daniel Borkowski, David Jewett, Michael Joseph Borruso
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Patent number: 10371287Abstract: Systems, methods, process, and article of manufacture regarding alignment orifice shields are provided. Shields can be configured to mate with leaching conduits in a certain configuration and can provide visual clues with regard to orientation as well as stability of installation for a pressurized or gravity-flow conduit. Methods of manufacture are also provided where manual or automated systems may be used for securing and adapting conduits to align with one or shields prior to or during installation of a leaching system.Type: GrantFiled: September 19, 2014Date of Patent: August 6, 2019Inventors: David A. Potts, Daniel Borkowski
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Publication number: 20180319686Abstract: Reconfigurable water leaching modules are provided herein. These modules may comprise a plurality of dosing conduits and a plurality of leaching channels fluidly coupled to the dosing conduits where the leaching channels are reconfigurable from a first retracted position to a second extended position and where the leaching channels may hang downwardly from the dosing conduits in the second extended position.Type: ApplicationFiled: April 26, 2018Publication date: November 8, 2018Inventors: David A. Potts, Daniel Borkowski, David Jewett, Michael Joseph Borruso
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Publication number: 20180044905Abstract: Wastewater leaching chambers and leaching channels are disclosed. The chambers may include a recess for receiving a wastewater supply, the recess serving to lower the overall height of the combined chamber and supply. The recess also configured to tightly seat the supply and form a gap therebetween. Leaching channels having a high aspect ratio may also be coupled to or otherwise in fluid communication with the chamber.Type: ApplicationFiled: August 15, 2017Publication date: February 15, 2018Inventors: David A. Potts, Daniel Borkowski, David Jewett
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Patent number: 9760409Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.Type: GrantFiled: May 24, 2016Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Chelsea Akturan, Avinash N. Ananthakrishnan
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Publication number: 20160266941Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.Type: ApplicationFiled: May 24, 2016Publication date: September 15, 2016Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
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Patent number: 9372524Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.Type: GrantFiled: December 15, 2011Date of Patent: June 21, 2016Assignee: Intel CorporationInventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
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Publication number: 20160084406Abstract: Systems, methods, process, and article of manufacture regarding alignment orifice shields are provided. Shields can be configured to mate with leaching conduits in a certain configuration and can provide visual clues with regard to orientation as well as stability of installation for a pressurized or gravity-flow conduit. Methods of manufacture are also provided where manual or automated systems may be used for securing and adapting conduits to align with one or shields prior to or during installation of a leaching system.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Applicant: Geomatrix, LLCInventors: David A. Potts, Daniel Borkowski
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Publication number: 20120144217Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.Type: ApplicationFiled: December 15, 2011Publication date: June 7, 2012Inventors: Krishnakanth V. Sistla, Mark Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Daniel Borkowski, Vivek Garg, Cagdas Akturan, Avinash N. Ananthakrishnan
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Publication number: 20060095559Abstract: According to some embodiments, an event flag signal generated by a network processor engine may be received at a co-processor. For example, a location in an event flag register at the co-processor may be set, and an event counter associated with that location may be incremented. The co-processor may also generate a notification signal in accordance with one or more locations in the event flag register and/or event counters.Type: ApplicationFiled: September 29, 2004Publication date: May 4, 2006Inventors: Peter Mangan, Daniel Borkowski
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Publication number: 20050149602Abstract: A method and apparatus to control interaction between two multi-threaded processor engines is presented. A first multi-threaded processor engine is configured for connection to a serial link, and performs receive and transmit operations in a first “PHY” mode of operation. A second multi-threaded processor engine is operable to process data received by the first multi-threaded processor over the serial link and to provide the processed data to the first multi-threaded processor engine for transmission over the serial link, when the first multi-threaded processor operates in the PHY mode. Additionally, the first multi-threaded processor engine is configured to execute certain operations, e.g., hardware accelerator operations, at the request of the second multi-threaded processor engine in a second “co-processor” mode of operation.Type: ApplicationFiled: December 16, 2003Publication date: July 7, 2005Inventors: Muthu Venkatachalam, Daniel Borkowski
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Publication number: 20050111475Abstract: A method and apparatus for remapping channel data are presented. Multiple successive frames carrying data in timeslots are received. The timeslots are assigned to channels so that data for the channels includes interleaved data. The data from the multiple successive frames for each of a predetermined number of the timeslots are aggregated. The aggregated data is mapped, by timeslot, to produce a timeslot-based map. The aggregated data of the timeslot-based map is remapped to produce a channel-based map in which the data for the channels are grouped together by channel in the order that the data were received.Type: ApplicationFiled: November 26, 2003Publication date: May 26, 2005Inventors: Daniel Borkowski, Nancy Borkowski
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Publication number: 20050071529Abstract: Systems and methods are disclosed for implementing software FIFOs on network processing engines (NPEs). The logic needed to support these software FIFOs is believed to be less than that needed to support additional hardware FIFOs, especially as the number of additional FIFOs is increased. Thus, the systems and methods enable NPEs to utilize more FIFOs at less cost. The counting semaphores that are used in the implementation of the software FIFOs can also, or alternatively, be used to provide NPEs with additional resource-locking and signaling functionality.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Applicant: Intel Corporation, a Delaware CorporationInventors: Daniel Borkowski, Nancy Borkowski
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Publication number: 20050053083Abstract: Systems and methods are disclosed for using High-level Data Link Control (HDLC) channel context information to simultaneously process multiple HDLC channels. Preferred embodiments of the present invention enable a single network processing engine to process multiple HDLC channels. The current state of the HDLC channel can be evaluated, stored, and restored, which means that the processing of a channel can be halted, the channel state read and stored, and the state of a different channel written to the processing engine. This allows the engine to begin processing a new channel, and then, at a later stage, restore the state of the original channel and resume processing.Type: ApplicationFiled: September 4, 2003Publication date: March 10, 2005Applicant: Intel CorporationInventors: Ronan O'Ceallaigh, Daniel Borkowski, Niall McDonnell
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Patent number: D646151Type: GrantFiled: November 19, 2010Date of Patent: October 4, 2011Assignee: Geomatrix, LLCInventors: David Potts, Daniel Borkowski, Nicholas Searles
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Patent number: RE44378Abstract: In a cellular system configuration, the location of a mobile station is determined from the acquisition of cellular network data pertaining to the mobile station, and the translation of such network data into a corresponding geographical position profile. The cellular system includes a mobile station locator entity for receiving from a mobile switching center the network data such as cell and/or sector ID and trunk group member number. The mobile station locator translates the network data into position information such as geographic coordinates (latitude and longitude), resolution (radius), and angle values for sectorized cells.Type: GrantFiled: September 25, 2006Date of Patent: July 16, 2013Assignee: Verizon Laboratories Inc.Inventors: Daniel Borkowski, Robert D. Packard, II, Hingsum F. Fung, Hadi F. Habal, Manuel Maseda, Sheng-Roan Kai, Kenneth Chao