Patents by Inventor Daniel Bourne

Daniel Bourne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908934
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani, Abhijit Jayant Pethe
  • Publication number: 20210159339
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 27, 2021
    Inventors: Anand S. MURTHY, Daniel Bourne AUBERTINE, Tahir GHANI, Abhijit Jayant PETHE
  • Patent number: 10957796
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani, Abhijit Jayant Pethe
  • Patent number: 8598003
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventors: Anand S. Murtthy, Daniel Bourne Aubertine, Tahir Ghani, Abhijit Jayant Pethe
  • Publication number: 20110147828
    Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Anand S. Murthy, Daniel Bourne Aubertine, Tahir Ghani, Abhijit Javant Pethe
  • Publication number: 20060246522
    Abstract: The present invention is directed towards the synthesis and/or use of a mixture of analyte capture reagents comprising antibodies and a non-immunological reagent provided on a solid phase assay, selected to screen for very high and low levels of an analyte. The non-immunological reagent comprising a PC-conjugate that contains multiple copies of covalently coupled phosphorylcholine (PC) moieties, particularly towards a phosphorylcholine-thyroglobulin conjugate assaying for C-reactive protein (CRP), a known inflammatory marker. The mixture of capture reagents function to eliminate hook effect (i.e. false negatives) when CRP is present in sample at high concentrations.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 2, 2006
    Inventors: Balwant Bhullar, Daniel Bourne
  • Publication number: 20060225483
    Abstract: The present invention includes methods of determining the volume of liquid dispensed by a dispenser. Initially, a refractive index analysis is preformed on a first liquid that has been dispensed from the dispenser in question. From the refractive index analysis, information is obtained about the volume of first liquid dispensed. The invention also includes methods for verifying the volumetric accuracy of a dispenser. The methods include dispensing a first liquid having a known refractive index into a vessel having a second liquid with a known volume and a known refractive index to form a test mixture. The refractive index of the test mixture is measured and then correlated with the refractive index of the first liquid to obtain information about the volume of first liquid dispensed. The dispensed volume is then compared to the theoretical volume of liquid dispensed by the dispenser.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 12, 2006
    Applicant: Streck, Inc.
    Inventors: Balwant Bhullar, Daniel Bourne