Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.

Abstract: Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.

Abstract: Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.

Abstract: The formation of substrate electrical connections on thin film heads is one source of resulting surface topography. In accordance with one implementation, such topography can be reduced by a process that includes depositing a first layer of basecoat, creating electrical recessed vias in one or more plating processes, and depositing a second layer of basecoat on top of the electrical vias and on top of the first layer of basecoat. In one implementation, the first and second layers of basecoat have a combined height that is substantially equal to the height of the electrical recessed vias. In one implementation, the resulting topographical features are small enough that they can be planarized without creating a lack of uniformity in the total basecoat thickness across the wafer.

Abstract: A system and method of operation for a lithographic system having multiple exposure stations sharing one or more post-expose bake station and a centralized control system that schedules work through the expose station to the post-expose bake station while taking into consideration the patterning time for work pieces to be scheduled as well as the amount of post-expose delay allowable for the exposed work pieces.

Abstract: The present invention comprises a system, software, and method for the treatment of mask data that produces defects in resultant images produced in the fabrication of a mask, following identification of the defects. The invention involves identifying each exposure shot with certain information which when combined with similar information related to the defects is used to control the exposure tool to toggle or modulate the shots related to the defects and thus, eliminate the defects.