Patents by Inventor Daniel C. Biederman
Daniel C. Biederman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9753674Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.Type: GrantFiled: May 9, 2016Date of Patent: September 5, 2017Assignee: VIOLIN MEMORY INC.Inventors: Jon C. R. Bennett, David M. Smith, Daniel C. Biederman
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Patent number: 9547588Abstract: Flash memory is subject to a wear out failure mechanism which may depend on the number of times each cell of the memory is programmed and erased. The higher the programming voltage used, the more rapidly the cell degrades. A system and method for reducing the average programming voltage for data sets is disclosed.Type: GrantFiled: September 9, 2014Date of Patent: January 17, 2017Assignee: VIOLIN MEMORY INC.Inventors: Daniel C. Biederman, Jon C. R. Bennett
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Patent number: 9513845Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.Type: GrantFiled: March 13, 2013Date of Patent: December 6, 2016Assignee: VIOLIN MEMORY INC.Inventors: Jon C. R. Bennett, Daniel C. Biederman
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Publication number: 20160337121Abstract: An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and a crypto engine coupled to the digital circuitry. Single interface and multiple interface schemes are provided to control both PHY and crypto functions. Embodiments are disclosed where the PHY controls the crypto device, and where the crypto device controls the PHY.Type: ApplicationFiled: August 24, 2014Publication date: November 17, 2016Inventors: Li-Jau Yang, Daniel C. Biederman
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Publication number: 20160253125Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Inventors: Jon C.R. Bennett, David M. Smith, Daniel C. Biederman
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Patent number: 9417823Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module. A plurality of groups of controllers may communicate with a switch or with a representative controller so as to coordinate the assignment of global sequence numbers.Type: GrantFiled: June 6, 2013Date of Patent: August 16, 2016Assignee: VIOLIN MEMORY INC.Inventors: Jon C. R. Bennett, Daniel C. Biederman, David M. Smith
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Patent number: 9361047Abstract: In a memory system where memory units may be separated from each other so as to operate substantially independently, the coordination of related memory operations between such units may be by synchronization of an epoch of time and the start of an epoch of time with a common synchronization source. The source may be distributed directly to each of the memory modules of a memory unit, or through an intermediate synchronization circuit of a memory unit that is common to the modules. Where the data is stored as a RAID stripe on a plurality of synchronized modules, the read and write or erase operations performed by the modules may be arranged such that the write operations or erase operations may not substantially affect the ability to promptly read the stored data of a RAID stripe.Type: GrantFiled: July 2, 2013Date of Patent: June 7, 2016Assignee: VIOLIN MEMORY INC.Inventors: Daniel C. Biederman, Jon C. R. Bennett
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Patent number: 9335939Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.Type: GrantFiled: July 11, 2012Date of Patent: May 10, 2016Assignee: VIOLIN MEMORY INC.Inventors: Jon C. R. Bennett, David M. Smith, Daniel C. Biederman
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Publication number: 20140362988Abstract: An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and a crypto engine coupled to the digital circuitry. Single interface and multiple interface schemes are provided to control both PHY and crypto functions. Embodiments are disclosed where the PHY controls the crypto device, and where the crypto device controls the PHY.Type: ApplicationFiled: August 24, 2014Publication date: December 11, 2014Inventors: Li-Jau Yang, Daniel C. Biederman
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Publication number: 20140365726Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module. A plurality of groups of controllers may communicate with a switch or with a representative controller so as to coordinate the assignment of global sequence numbers.Type: ApplicationFiled: June 6, 2013Publication date: December 11, 2014Inventors: Jon C.R. Bennett, Daniel C. Biederman, David M. Smith
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Patent number: 8843735Abstract: An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and a crypto engine coupled to the digital circuitry. Single interface and multiple interface schemes are provided to control both PHY and crypto functions. Embodiments are disclosed where the PHY controls the crypto device, and where the crypto device controls the PHY.Type: GrantFiled: April 1, 2010Date of Patent: September 23, 2014Assignee: Cisco Technology, Inc.Inventors: Li-Jau Yang, Daniel C. Biederman
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Publication number: 20140013048Abstract: In a memory system where memory units may be separated from each other so as to operate substantially independently, the coordination of related memory operations between such units may be by synchronization of an epoch of time and the start of an epoch of time with a common synchronization source. The source may be distributed directly to each of the memory modules of a memory unit, or through an intermediate synchronization circuit of a memory unit that is common to the modules. Where the data is stored as a RAID stripe on a plurality of synchronized modules, the read and write or erase operations performed by the modules may be arranged such that the write operations or erase operations may not substantially affect the ability to promptly read the stored data of a RAID stripe.Type: ApplicationFiled: July 2, 2013Publication date: January 9, 2014Inventors: Daniel C. Biederman, Jon C.R. Bennett
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Publication number: 20130262739Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.Type: ApplicationFiled: March 13, 2013Publication date: October 3, 2013Inventors: Jon C.R. Bennett, Daniel C. Biederman
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Publication number: 20130019062Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.Type: ApplicationFiled: July 11, 2012Publication date: January 17, 2013Applicant: Violin Memory Inc.Inventors: Jon C.R. Bennett, David M. Smith, Daniel C. Biederman
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Patent number: 7860125Abstract: In an example embodiment, an apparatus comprising a physical layer processing device that comprises logic configured to process a packet received from a physical layer interface is disclosed. The physical layer processing device logic is further configured to determine a preamble portion of the packet and a data portion of the packet. The physical layer processing device logic is further configured to insert a timestamp into the preamble portion of the packet. The physical layer processing device logic forwards the packet with the timestamp inserted into the preamble.Type: GrantFiled: January 28, 2008Date of Patent: December 28, 2010Assignee: Cisco Techology, Inc.Inventors: Amrik Bains, Daniel C. Biederman, Darrell Rice Heflin, Norman William Finn, Krishna Kondaka, Peter Geoffrey Jones
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Publication number: 20100191956Abstract: An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and a crypto engine coupled to the digital circuitry. Single interface and multiple interface schemes are provided to control both PHY and crypto functions. Embodiments are disclosed where the PHY controls the crypto device, and where the crypto device controls the PHY.Type: ApplicationFiled: April 1, 2010Publication date: July 29, 2010Applicant: CISCO TECHNOLOGY, INC.Inventors: Li-Jau Yang, Daniel C. Biederman
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Patent number: 7730202Abstract: A method of adjusting a timer is disclosed. The method includes adjusting a timer activation period based on a characteristic of a network and setting the timer using the timer activation period. The timer is used in communicating information over the network.Type: GrantFiled: July 16, 2001Date of Patent: June 1, 2010Assignee: Cisco Technology, Inc.Inventors: Daniel C. Biederman, Malathy Sethuraman, Jeffrey P. Chou
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Patent number: 7710974Abstract: Methods and apparatus are disclosed for dynamically allocating bandwidth to a plurality of client devices coupled over a network to a physical layer device (PHY). The PHY is preferably configured to utilize a connection criteria, such as bandwidth requirement for the client devices, to negotiate and connect the devices to a host device in a desired order.Type: GrantFiled: August 12, 2004Date of Patent: May 4, 2010Assignee: Cisco Technology, Inc.Inventor: Daniel C. Biederman
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Patent number: 7711948Abstract: An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and a crypto engine coupled to the digital circuitry. Single interface and multiple interface schemes are provided to control both PHY and crypto functions. Embodiments are disclosed where the PHY controls the crypto device, and where the crypto device controls the PHY.Type: GrantFiled: September 30, 2003Date of Patent: May 4, 2010Assignee: Cisco Technology, Inc.Inventors: Li-Jau Yang, Daniel C. Biederman
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Publication number: 20090190589Abstract: In an example embodiment, an apparatus comprising a physical layer processing device that comprises logic configured to process a packet received from a physical layer interface is disclosed. The physical layer processing device logic is further configured to determine a preamble portion of the packet and a data portion of the packet. The physical layer processing device logic is further configured to insert a timestamp into the preamble portion of the packet. The physical layer processing device logic forwards the packet with the timestamp inserted into the preamble.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Inventors: Amrik Bains, Daniel C. Biederman, Darrell Rice Heflin, Norman William Finn, Krishna Kondaka, Peter Geoffrey Jones