Patents by Inventor Daniel C. Espinosa

Daniel C. Espinosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Radiation hardened 10BASE-T ethernet physical layer (PHY)
    Patent number: 9680527
    Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: June 13, 2017
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Michael R. Lin, David J. Petrick, Kevin M. Ballou, Daniel C. Espinosa, Edward F. James, Matthew A. Kliesner
  • Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)
    Publication number: 20160248477
    Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.
    Type: Application
    Filed: September 16, 2015
    Publication date: August 25, 2016
    Inventors: MICHAEL R. LIN, DAVID J. PETRICK, KEVIN M. BALLOU, DANIEL C. ESPINOSA, EDWARD F. JAMES, MATTHEW A. KLIESNER
  • Radiation-hardened processing system
    Patent number: 8484509
    Abstract: A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: July 9, 2013
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics Space Administration
    Inventors: Daniel C. Espinosa, Alessandro Geist, David J. Petrick, Thomas P. Flatley, Jeffrey C. Hosler, Gary A. Crum, Manuel Buenfil
  • RADIATION-HARDENED PROCESSING SYSTEM
    Publication number: 20110107158
    Abstract: A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.
    Type: Application
    Filed: August 11, 2010
    Publication date: May 5, 2011
    Inventors: Daniel C. Espinosa, Alessandro Geist, Daivd J. Petrick, Thomas P. Flatley, Jeffrey C. Hosler, Gary A. Crum, Manuel Buenfil