Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.

Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.

Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.

Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.

Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.

Abstract: Sheet resistance of titanium silicide formed on silicon is diminished by enhancing formation of nucleation sites for the C-54 phase. Fluorine is introduced into silicon by either the implantation of BF.sub.2 or F, followed by creation of a cap oxide over the silicon surface. During subsequent annealing, fluorine outgasses, forming bubbles in the silicon. Upon removal of the cap oxide, the gas escapes and the silicon surface is pitted and uneven, enhancing subsequent formation of C-54 nucleation sites.

Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.