Abstract: A method of controlling an actuator in a disc drive to move a data head to implement an access in accordance with the invention includes determining a first rotational position corresponding to a rotational position of the data head when the access will start and determining a second rotational position corresponding to a rotational position of the data head at a destination of the access. Subsequently, an access time required to move the data head from the first rotational position on a current or initial track to the second rotational position on a destination track using a fastest of multiple seek profiles is determined. A slower or slowest of the multiple seek profiles which can be used to move the data head from the first track to the second track within the access time is determined. Subsequently, the actuator is controlled using the determined slower or slowest of the multiple seek profiles to implement the access. In addition, a disc drive is provided.

Abstract: Disclosed is an arrangement for "seamlessly" integrating telephone services relative to primitive analog telephone equipment into general purpose computer systems. The integration is effected through present "secondary" adaptation of data link control adapter devices which are adapted primarily for coupling such computer systems to high speed data communication links for transmission and reception of digital data. This permits general resources of the computer system (keyboard, memory, disk drives, etc.) to be used for specific applications associated with telephone services. Presently described link control devices have a telephone attachment port which couples through analog-to-digital conversion circuits to a primitive analog telephone (no dial or keys). Such devices operate normally in time division multiplex to process communication data between a computer (host) system and data link ports.

Abstract: Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot.

Abstract: A "single-chip" integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes.

Abstract: An integrated data link control device (IDLC) interfaces between a host computer system and external channels in a communication network. The device contains multiple internal channels allocatable individually to interface to the external channels, each internal channel having internal buffer memory reserved to it for storing data signals handled by it. The device also includes facilities for selectively configuring groups of its internal channels into "extended channels", some of which are termed Hyper Channels. Channels in each extended channel group interface collectively and in time coordination to one external channel, presenting an effective bandwidth to the external channel which is greater than the bandwidth of any single internal channel.

Abstract: An improved multi-channel direct memory access (DMA) controller for data processing systems provides adaptive pipelining and time overlapping of operations performed relative to communication channels. Registers and resources used to pipeline communication data and control signals relative to plural channels are adaptively shared relative to a single channel when command chaining is required relative to that channel. In command chaining a plural word command, termed a Device Control Block (DCB), is fetched from an external system memory via a bus having severe time constraints relative to potential real time requirements of the channels. Pipelining and time overlapping of channel operations, relative to plural channels, increases the effective rate of transfer at the bus interface to the system memory, and thereby allows for the controller to be used for applications in which throughput requirements and bus access constraints could otherwise conflict.

Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface.