Abstract: A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: A method and apparatus for conducting transition testing using scan elements are disclosed. In one embodiment, an integrated circuit (IC) includes a scan chain having first and second subsets of scannable flops, the first subset having respective data inputs coupled to a memory array. The scannable flops of the second subset may each have a respective data input coupled to circuitry other than the memory array (e.g., to a logic circuit). The scannable flops of the first subset may be enabled for scan shifting during a transition test mode. The scannable flops of the second subset are inhibited from scanning during the transition test mode. The transition test mode may include at least two functional clock cycles in which the scannable flops of the first subset provide complementary first and second logic values to logic circuits coupled to respective data outputs.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Abstract: In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.

Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.

Abstract: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.

Abstract: In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first plurality has an N-bit input coupled to the output of the accumulator. A second plurality of the plurality of N-bit 3:2 carry save adders have inputs coupled to outputs of the first plurality, and a most significant bit of each carry output of the first plurality is inserted as a least significant bit of the carry output at the input to the second plurality.