Abstract: A memory management system for use with a logic simulator 10 for storing data in each memory that is being simulated by the logic simulator 10. The system includes memory control logic 14 coupled to a physical memory 16 which is segmented into a permanent storage area P (26), a temporary storage area T1 (24) and a second temporary storage area T2 (22). Each write request from the simulator causes memory control logic 14 to store the latest request into the T2 area (22). Prior data stored in T2 (22) are first moved to the T1 (24) or P (26) storage area where other store requests for the same and other simulated locations were stored during the same simulator time interval. In this fashion, a history of simulator write activity is stored in physical memory 16 and available for rerunning or restarting the simulator 10 at or near a prior simulator cycle.

Abstract: A memory management system for use with a logic simulator 10 for storing data in each memory that is being simulated by the logic simulator 10. The system includes memory control logic 14 coupled to a physical memory 16 which is segmented into a permanent storage area P (26), a temporary storage area T1 (24) and a second temporary storage area T2 (22). Each write request from the simulator causes memory control logic 14 to store the latest request into the T2 area (22). Prior data stored in T2 (22) are first moved to the T1 (24) or P (26) storage area where other store requests for the same and other simulated locations were stored during the same simulator time interval. In this fashion, a history of simulator write activity is stored in physical memory 16 and available for rerunning or restarting the simulator 10 at or near a prior simulator cycle.

Abstract: A simulator system of a digital network which may contain a memory. The system includes at least three hierarchical data storage buffers 18, 20, 24, 26 for storing the simulated network signals for simulated registers and combinatorial logic at the close of each simulation cycle. Each buffer 20, 24, 26 has a plurality of entries comprising a periodic sampling, sometimes referred to as checkpointing, of the next lower storage buffer. The system also includes a change management list 30 and a memory data array 32 for respectively storing time/address pairs and time/value pairs to identify the time, address and value of memory writes. These pairs of data are updated (i.e., checkpointed) each time a selected data storage buffer 24, 26 starts to have previously written locations overwritten by newer data.