Abstract: Described are automated systems and methods for providing a simulated environment for robotic and/or real-time systems, such as unmanned vehicles, to perform full system simulations while also providing a system-wide code coverage assessment of the software associated with the robotic and/or real-time systems. The exemplary systems and methods can employ code coverage instrumented shared libraries to facilitate generation of code coverage information and one or more code coverage reports. The code coverage information and/or the code coverage report can quantify the effectiveness of the testing and can facilitate development of more comprehensive and efficient testing of the software.

Abstract: In various embodiments, methods and systems for maintaining compatibility between applications, based on feature-set constraints are provided. A distributed computing system provides Platform as a service (PaaS) including a software framework in a service model of cloud computing. A known compatibility baseline is established for features of a first application and a second application. The known compatibility baseline inherently includes a baseline set of unenumerated features of the applications. It is determined that the first application is compatible with second application based on comparing an explicit enumeration of added features or removed features in a feature set of the applications. The added features or removed features are tracked after the baseline set of unenumerated features is defined. The determination whether the first application and the second application are compatible is communicated for processing the first application and/or the second application.

Abstract: Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

Abstract: In various embodiments, methods and systems for maintaining compatibility between applications, based on feature-set constraints are provided. A distributed computing system provides Platform as a service (PaaS) including a software framework in a service model of cloud computing. A known compatibility baseline is established for features of a first application and a second application. The known compatibility baseline inherently includes a baseline set of unenumerated features of the applications. It is determined that the first application is compatible with second application based on comparing an explicit enumeration of added features or removed features in a feature set of the applications. The added features or removed features are tracked after the baseline set of unenumerated features is defined. The determination whether the first application and the second application are compatible is communicated for processing the first application and/or the second application.

Abstract: A dynamically variable source resistance is provided for each sector of a NOR-type Flash memory device. The variable source resistance of a given sector is set to a relatively low value (i.e., close to zero) during read operations. The variable source resistance is set to a relatively high impedance value (i.e., close to being an open circuit) during flash erase operations. The variable source resistance is set to a first intermediate resistance value at least during soft-programming where the first intermediate resistance value is one that raises VS and thus drives VGS below local threshold even for over-erased transistors of the sector that have a VGoff de-assertion voltage applied to their control gates for purpose of turning those transistors off. In one embodiment, the variable source resistance is set to a second intermediate resistance value during a testing mode that tests the extent to which the corresponding sector has been over-erased.

Abstract: Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Abstract: A metal-to-metal antifuse according to the present invention is compatible with a Cu dual damascene process and is formed over a lower Cu metal layer planarized with the top surface of a lower insulating layer. A lower barrier layer is disposed over the lower Cu metal layer. An antifuse material layer is disposed over the lower barrier layer. An upper barrier layer is disposed over the antifuse material layer. An upper insulating layer is disposed over the upper barrier layer. An upper Cu metal layer is planarized with the top surface of the upper insulating layer and extends therethrough to make electrical contact with the upper barrier layer.