Abstract: Disk drives are mirrored through duplication controlled by disk controllers. Each disk controller controls writing to a set of disk drives. A disk write request to one disk controller causes that disk controller to write to one of its disks and to transmit the write request to another controller that in turn writes to its disk. The second controller then acknowledges the write to the first controller, which in turn acknowledges the write to the computer issuing the request. The first controller further logs the writes in a log file. This allows efficient resynchronization after mirroring is broken and reestablished, as well as removing cable length restrictions between controllers.

Abstract: A power distribution unit (PDU) for supplying power to at least one electrical device (APP1-APP12), comprises at least one distribution point (P) for the power supply, and at least one female outlet (J1-J12) on its accessible side. The outlet is adapted to receive a male connector of a cable of an electrical device (APP1-APP12). The point (P) is electrically connected by a respective electrical cable to at least one manually resettable circuit breaker (BRK1-BKR6). The at least one circuit breaker comprises a respective push button (POU1-POU6) for resetting the circuit breaker. The circuit breaker (BRK1-BRK6) is connected by a respective electrical cable to the at least one female outlet (J1-J12). The circuit breaker (BRK1-BRK6) is located inside the unit and at least one reset mechanism capable of resetting the at least one circuit breaker is provided. Several circuit breakers may be supported in line and the reset mechanism is capable of resetting all of the circuit breakers simultaneously.

Abstract: A disk cache device for secure writing comprising a backup power supply source (62) for supplying backup power for a given duration to a computer system fed by two main electric power supply devices (60, 61) and comprising at least one hard disk drive (1a, 1b, 1c), and a host system (3). All of the disk drives (1a, 1b, 1c) are linked by a bus (2) to a connection (30) of the host system (3) (host bus adapter), and a monitor (50) for monitoring at least the backup electric power supply source (62) and the main power supply devices (60, 61). Monitors (50) are connected to the interface (2) and can be interrogated by an interrogator (31) for interrogating the host system (3) so that the latter can enable the write disk cache function, or not, in the write commands to be sent to the disk drives (1a, 1b, 1c) in accordance with the information gathered by the monitoring means (50).

Abstract: A mass memory storage unit includes a cabinet and one or more drawers incorporated into the cabinet. Each drawer is movable between closed and open positions to permit access to the interior for service. Inside each drawer, there is a connector plane disposed generally to one side of the drawer interior and parallel to the direction of travel between the closed and open positions. The connector plane incorporates connectors for receiving storage devices (for example, hard disk drives), each incorporating a connector which detachably mates with one of the connectors on the connector plane. Support and interface devices are coupled to the connector plane by suitable complementary connectors. It is useful to provide a cable, which itself may be detachable from the connector plane, to establish a redundant connection such that the devices in a drawer remain in-circuit when that drawer is opened for access to the enclosed components.

Abstract: The present invention relates to a disk storage subsystem with multiple configurable interfaces, characterized in that it comprises at least one interface adapter board (1a, 1b), at least one drawer (4), each comprising a plurality of disks (20), each drawer (4) being connected to an adapter board (1a or 1b) by SCSI disk interfaces (2), a first adapter board (1a or 1b) comprising a switch (11) for modifying the addressing system of the disks (20) of at least one drawer (4), the adapter board or boards (1a, 1b) each comprising two independent single-ended/differential-ended SE/DE converters (7), each SE/DE converter (7) being connected to a drawer (4) and fed by either of two direct current/direct current DC/DC converters (7) of the adapter board (1), and two external SCSI connectors (10) being connected to each SE/DE converter (7).

Abstract: Disk drives are mirrored through duplication controlled by disk controllers. Each disk controller controls writing to a set of disk drives. A disk write request to one disk controller causes that disk controller to write to one of its disks and to transmit the write request to another controller that in turn writes to its disk. The second controller then acknowledges the write to the first controller, which in turn acknowledges the write to the computer issuing the request. The first controller further logs the writes in a log file. This allows efficient resynchronization after mirroring is broken and reestablished, as well as removing cable length restrictions between controllers.

Abstract: Power distribution unit (PDU) for supplying power to at least one electrical device (APP1-APP12), comprising at least one distribution point (P) for the power supply, and at least one female outlet (J1-J12) on its side designed to receive a male connector of a cable of an electrical device (APP1-APP12), said point (P) being electrically connected by means of a respective electrical cable to at least one manually resettable circuit breaker (BRK1-BKR6), said at least one circuit breaker comprising a respective push button (POU1-POU6) for resetting it, a circuit breaker (BRK1-BRK6) being connected by means of a respective electrical cable to at least one female outlet (J1-J12), characterized in that said at least one circuit breaker (BRK1-BRK6) is located inside the unit, and in that it comprises at least one reset mechanism capable of resetting said at least one circuit breaker.

Abstract: A data processing system with a RAID cache disk subsystem utilizes three RAID cache disk controllers to provide increased performance along with increased reliability, especially in the event of a failure of one of the disk controllers. Disk writes are mirrored in two disk controllers in order to guarantee integrity in the event of a disk controller or interface failure. Typically this write caching must be terminated when one of the controllers fails in order to maintain integrity. In the present invention, write caching continues utilizing the two remaining disk controllers.

Abstract: A multidisk storage system (SD) equipped with a redundancy mechanism comprises at least two disk units (UND1-UND3), at least one redundancy control unit (UNC1-UNC2), a power distribution point (P), and a control unit (EG1-EG5), located in proximity to the point (P), for triggering the opening of the corresponding line (LI1-LI5) in case of an electrical fault in the associated unit and in the line itself. This system therefore ensures an optimal protection against electrical faults and ensures an optimal availability of the data.

Abstract: In order to obtain mixed and space efficient use of mass memory units having different form factors into a single package, a specially configured connector plane module is provided. The connector plane module includes three identical, aligned, connector plane connectors arranged in a new configuration. Two spaced apart connector plane connectors are disposed in the same orientation with one another; but the third connector plane connector is spaced apart from and disposed in 180° orientation with respect to the second connector. With this configurtion, two mass memory storage units having a first form factor or three mass memory storage units of a second, smaller, form factor may be coupled to the connector plane to occupy substantially the same space, one mass memory unit in each case being oriented at 180° with respect to the one or two other mass memory units.

Abstract: An add-on device (DHD) for disk drives (D) for a multidisk system containing a plurality of drawers (T) includes a metal base support (S) for a disk drive (D), an opening (O) into which an external connector (CN) of the device is inserted, a mechanism for inserting, extracting and locking (PO, R, R1-R2) the device in a selected slot of the drawer, air passages for ventilating the disk drive, a first printed circuit board (CCE) for interconnecting the disk drive with its external environment, and a second board (CCT) connected to the first printed circuit board for supporting DC voltage conversion functions.

Abstract: An apparatus (T) for housing a mass memory subsystem (SSM.sub.1 -SSM.sub.3) that is connected to at least one host system (H.sub.1, H.sub.2) is provided. The apparatus includes a plurality of compartments, each compartment receiving at least one of a plurality of groups of disk units (101-112, 201-212, . . . , 601-612); at least one electrical supply unit for supplying electrical power to the disk units; a plurality of plates (P1-P6) having a central portion about which the compartments are arranged. The compartments carry the disk units. The central portion includes an electronic card to which the disk units are connected. The electronic card provides real-time management of disk units and connection of the disk units to the host system. The apparatus has a front portion (PAV) adapted to house the plurality of plates that are slidably insertable into the front portion and are arranged parallel to each other.

Abstract: A dual-access protected electronic mass memory unit, the various elements of which comprise a plurality of logic boards connected to at least one peripheral controller (CNT.sub.1, CNT.sub.2) of the information processing system (H) to which the unit belongs. The electronic memory unit includes at least one electronic disk unit (DEI.sub.1, DEI.sub.2) including a motherboard (11, 21) containing the corresponding controller (CNT.sub.1, CNT.sub.2), and a plurality of daughter boards (12-13, 22-23) comprising an equal number of memory planes connected among one another two-by-two, the first of them being connected to the motherboard. The central processor and the electronic disk unit are connected by the motherboard to a first and second parallel bus (B.sub.1, B.sub.2).

Abstract: A peripheral mass memory subsystem (PSS.sub.1, PSS.sub.2) of an information processing system including at least one central host (H.sub.1, H.sub.2, H.sub.4, H.sub.4), two control units (UC.sub.1, UC.sub.2) and at least one mass memory (BMD.sub.1, BMD.sub.2, . . . ,) with independent electrical power supplies (ALIM.sub.1, ALIM.sub.2, BAT.sub.1, BAT.sub.2) and each having a plurality of structural (hardware+microsoftware) elements (PR.sub.1 -PR.sub.2, DE.sub.1 -DE.sub.2, CA.sub.1 -CA.sub.2, HA.sub.1 -HA.sub.2, DA.sub.1 -D.sub.2) connected to a first and/or a second parallel-type bus (B.sub.1, B.sub.2). The subsystem is characterized in that it includes a microsoftware architecture (AML) that executes the commands of the host and informs the host of changes in state of the mass memory and is embodied by a plurality of functional microsoftware subassemblies (P, H, D, C, S), each of them specific to each structural element of each control unit and implemented in its hardware structure.

Abstract: A protected method of fast writing of information for at least one mass memory apparatus (DMM.sub.1) belonging to an information processing system including at least one central host (H.sub.1, H.sub.2), two control units (UC.sub.1, UC.sub.2) with independent electrical power supplies (ALIM.sub.1, ALIM.sub.2, BAT.sub.1, BAT.sub.2) connected to a first and second parallel bus (B.sub.1, B.sub.2) is disclosed wherein the method is characterized in that, if the host (H.sub.1, H.sub.2) is connected to each of the two buses via at least one first host adaptor (HA.sub.1, HA.sub.2) belonging to the first control unit (UC.sub.1, UC.sub.2) and the mass memory (D.sub.1 -D.sub.5) is connected to each of the two buses via a first and a second mass memory adaptor (DA.sub.1, DA.sub.2) belonging to the first and second control unit, respectively, which include a first and a second memory buffer (MTD.sub.1, MTD.sub.2), respectively,I--the block of data to be written is memorized in the first host buffer (MTH.sub.1, MTH.sub.

Abstract: An information processing system architecture (ORDI), in which the various constituent elements (B.sub.1 -B.sub.6, A.sub.1 -A.sub.6, C.sub.1 -C.sub.4) comprise a plurality of boards (CDI.sub.i and CGI.sub.j), each embodied by printed circuits carrying a plurality of integrated circuits, and including at least two sets of elements (ENSI.sub.1, ENSI.sub.2), all or some of the elements of one set being identical to all or some of the elements of the other. The sets are associated with two system buses of the parallel type (PSBA, PSBBI) that assure both communications and the transfer of data and electrical energy among the boards. The two buses have a total or partial overlap zone (ZC) between them, on which either one or more elements (C.sub.1 -C.sub.2, C.sub.3 -C.sub.4) common to the two sets exclusively, and elements belonging to the first set (ENSI.sub.1, A.sub.5 and A.sub.6) and/or to the second set (ENSI.sub.2, B.sub.5 and B.sub.6), are connected.

Abstract: A DC motor drives a magnetic disk memory transducer head between a position proximate the disk periphery to an area on the disk where data are located during which time the head is lowered from an idle to a hovering position. During this time the motor is supplied with a current impulse having a predetermined polarity, amplitude and duration. The polarity of the current impulse is opposite to that of current applied to the motor while the head is being driven between a position beyond the disk periphery to the position proximate the disk periphery. The duration and amplitude of the current impulse are such that the motor angular velocity has a zero value at the completion of the current pulse. Thereafter, a ramping voltage having an average linear waveform is applied to the motor to prevent overshoot of the motor speed and prevent oscillation of the head relative to a face of the disk. The linear ramp current decreases to a zero value, at which time the motor has a constant, non-zero angular velocity.

Abstract: A magnetic disk memory is moved between a first position beyond the disk periphery to a second position proximate the disk periphery while the head is at an idle height above the disk face. The head is moved between the disk periphery and a third position at the edge of an area on the disk where data are located while the head is lowered and raised between the idle height and a hovering height above a face of the disk. An assembly carrying the head includes a radially extending arm, turned by a rotary DC motor. A continuous step excitation waveform is supplied to the motor as the head is driven between the first and second positions until the head arrives at one of the two positions. Each of the steps has a constant amplitude that differs from the immediately preceding step by a predetermined incremental value. All of the steps, except the last step, has the same predetermined duration.