Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.

Abstract: Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

Abstract: Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

Abstract: A mold tool (40) includes a lower platen (10) and an upper platen (18) which have modified surfaces (16) and (20), respectively. The modified surfaces are formed by implanting an implant species (14) at least into areas of the platens which will be in contact with a molding compound resin. By modifying the surface of the molding tool by ion implantation, the need for cleaning the mold tool is reduced due to lower surface friction and wettability of the modified surfaces. These surface characteristics also facilitate easier release of the molded package from the tool. At the same time, wear resistance of the mold tool is improved due to increased surface hardness.

Abstract: Advances in wafer technology and packaging have led to an increase in wafer size while requiring a decrease in wafer thickness. Thickness limitations increase as wafer diameter increases. Thinning a wafer past a certain limit can result in wafer breakage. A laminated semiconductor wafer structure (10) is assembled to provide mechanical support for the wafer. A semiconductor wafer (12) is affixed to a UV transparent support substrate (16) with a double-sided adhesive tape (14). The tape has dissimilar adhesives on its two sides. The first side has a UV curable adhesive (22) that adheres to the active surface of the wafer. The second side has a non-UV curable adhesive (24) which adheres to the UV transparent support substrate. This laminated structure can be used during a wafer thinning process and any subsequent handling. The support substrate and the tape are removed from the wafer by exposing the laminated structure to UV radiation.

Abstract: A plastic land grid array semiconductor device (30) can be manufactured using conventional techniques. In one embodiment, a semiconductor die (12) having an active surface is provided. An LOC leadframe (14) is provided, wherein leads (16) have a horizontal portion (18) and a vertical portion (20). The active surface of the die is attached to the leads with an LOC tape (17) and is electrically connected to the horizontal portion by wire bonds (24). A plastic package body (32) is molded around the die, the wire bonds, and a portion of the leadframe. The vertical portion of the leads terminates and its thickness is exposed at a surface of the package body, thus forming a grid array of external electrical contacts. An insulative material (34) is coated on the sides of the package body to cover any exposed thickness of the horizontal portion of the leads.