Patents by Inventor Daniel Chanemougame

Daniel Chanemougame has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002862
    Abstract: A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 4, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin
  • Patent number: 12002869
    Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: June 4, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
  • Patent number: 11961802
    Abstract: A semiconductor device includes a device plane including an array of cells each including a transistor device. The device plane is formed on a working surface of a substrate and has a front side and a backside opposite the front side. A signal wiring structure is formed on the front side of the device plane. A front-side power distribution network (FSPDN) is positioned on the front side of the device plane. A buried power rail (BPR) is disposed below the device plane on the backside of the device plane. A power tap structure is formed in the device plane. The power tap structure electrically connects the BPR to the FSPDN and electrically connects the BPR to at least one of the transistor devices to provide power to the at least one of the transistor devices.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 16, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin
  • Patent number: 11923364
    Abstract: A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: March 5, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin
  • Publication number: 20240047342
    Abstract: A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/ID structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, Hiroaki NIIMI, Kandabara TAPILY, Daniel CHANEMOUGAME, Lars LIEBMANN
  • Publication number: 20230411298
    Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.
    Type: Application
    Filed: August 30, 2023
    Publication date: December 21, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Daniel CHANEMOUGAME, Lars LIEBMANN, Jeffrey SMITH
  • Publication number: 20230395502
    Abstract: An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 7, 2023
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Geng Han
  • Patent number: 11830852
    Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: November 28, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Cline, Xiaoqing Xu, David Pietromonaco
  • Patent number: 11791263
    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: October 17, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Geng Han
  • Patent number: 11791271
    Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith
  • Publication number: 20230326855
    Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 12, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Lars LIEBMANN, Jeffrey SMITH, Daniel CHANEMOUGAME, Anton J. DEVILLIERS
  • Patent number: 11764113
    Abstract: Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: September 19, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Robert Clark, Anton Devilliers
  • Patent number: 11764266
    Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: September 19, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin
  • Patent number: 11735525
    Abstract: A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 22, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Lars Liebmann, Jeffrey Smith, Anton Devilliers, Daniel Chanemougame
  • Patent number: 11723187
    Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: August 8, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Paul Gutwin, Lars Liebmann, Daniel Chanemougame
  • Publication number: 20230223404
    Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Inventors: Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin
  • Publication number: 20230207566
    Abstract: In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Daniel CHANEMOUGAME, Lars LIEBMANN, Jeffrey SMITH
  • Patent number: 11665878
    Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the at least six transistors being lateral transistors with channels formed from nano-sheets grown by epitaxy. The at least six transistors positioned in two decks in which a second deck is positioned vertically above a first deck relative to a working surface of the substrate, wherein at least one NMOS transistor and at least one PMOS transistor share a common vertical gate. A first inverter formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in either the first deck or the second deck.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 30, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith
  • Patent number: 11646318
    Abstract: In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: May 9, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith
  • Patent number: 11631671
    Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 18, 2023
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Anton J. Devilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann, Subhadeep Kal