Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

Abstract: One illustrative method disclosed herein may include forming a contact etching structure in a layer of insulating material positioned above first and second lower conductive structures, wherein at least a portion of the contact etching structure is positioned laterally between the first and second lower conductive structures, forming a first conductive line and a first conductive contact adjacent a first side of the contact etching structure and forming a second conductive line and a second conductive contact adjacent a second side of the contact etching structure, wherein a spacing between the first and second conductive lines is approximately equal to a dimension of the contact etching structure.

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

Abstract: One illustrative method disclosed herein may include forming a contact etching structure in a layer of insulating material positioned above first and second lower conductive structures, wherein at least a portion of the contact etching structure is positioned laterally between the first and second lower conductive structures, forming a first conductive line and a first conductive contact adjacent a first side of the contact etching structure and forming a second conductive line and a second conductive contact adjacent a second side of the contact etching structure, wherein a spacing between the first and second conductive lines is approximately equal to a dimension of the contact etching structure.

Abstract: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.

Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

Abstract: An IC product disclosed herein includes a first merged doped source/drain (MDSD) region having an upper surface, a first side surface and a second side surface that intersect one another at a corner of the first merged doped source/drain region, a second MDSD region and a contact trench in an isolation structure positioned between the first and second MDSD regions. The product also includes a conductive gate structure positioned above at least the second MDSD region and a cross-coupled contact structure that comprises a first portion positioned within the contact trench laterally adjacent to and conductively coupled to at least one of the first side surface and the second side surface, and a second portion that is positioned above and conductively coupled to the upper surface of the MDSD region, wherein the cross-coupled contact structure is conductively coupled to the conductive gate structure.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

Abstract: A method includes forming a first gate structure above a first region of a semiconducting substrate. A first sidewall spacer is formed adjacent the first gate structure. The first gate structure and the first sidewall spacer are recessed to define a first gate contact cavity. A second sidewall spacer is formed in the first gate contact cavity. A first conductive gate contact is formed in the first gate contact cavity. The second sidewall spacer is removed to define a first spacer cavity. A conductive material is formed in the first spacer cavity to form a first conductive spacer contacting the first conductive gate contact.

Abstract: Disclosed are integrated circuit (IC) structure embodiments that incorporate a stacked pair of field effect transistors (FETs) (e.g., gate-all-around FETs) and metal components that enable power and/or signal connections to source/drain regions of those FETs. Specifically, the IC includes a first FET and a second FET stacked on and sharing a gate with the first FET. The metal components include an embedded contact in a source/drain region of the first FET and connected to a wire (e.g., a power or signal wire). The wire can be a front end of the line (FEOL) wire positioned laterally adjacent to the source/drain region and the embedded contact can extend laterally from the source/drain region to the FEOL wire. Alternatively, the wire can be a back end of the line (BEOL) wire and an insulated contact can extend vertically from the embedded contact through the second FET to the BEOL wire.

Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Abstract: Fabricating a negative capacitance steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin, a source/drain, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, and an inter-layer dielectric. A source/drain recess is formed in the inter-layer dielectric extending to the trench contact, and a gate recess is formed in the inter-layer dielectric extending to the gate. A ferroelectric material is deposited within the gate recess, and a source/drain contact is formed within the source/drain recess. A gate contact is formed within the gate recess, and a contact recess is formed in a portion of the source/drain contact. A bi-stable resistive system (BRS) material is formed in the contact recess, and a metallization layer contact is formed upon the BRS material. A portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forms a reversible switch.