Abstract: Embodiments of a Surface Acoustic Wave (SAW) device, or filter, and methods of fabrication thereof are disclosed. In some embodiments, the SAW filter comprises a piezoelectric substrate and an Interdigitated Transducer (IDT) on a surface of the piezoelectric substrate. The IDT includes multiple fingers, each comprising a metal stack. The SAW filter further includes a cap layer on a surface of the IDT opposite the piezoelectric substrate and on areas of the surface of the piezoelectric substrate exposed by the IDT. The cap layer has a thickness in a range of and including 10 to 500 Angstroms and a high electrical resistivity (and thus a low electrical conductivity). For instance, in some embodiments, the electrical resistivity of the cap layer is greater than 10 kilo-ohm meters (K?·m). The SAW filter further includes an oxide overcoat layer on a surface of the cap layer opposite the IDT and the piezoelectric substrate.

Abstract: Embodiments of a Surface Acoustic Wave (SAW) device, or filter, and methods of fabrication thereof are disclosed. In some embodiments, the SAW filter comprises a piezoelectric substrate and an Interdigitated Transducer (IDT) on a surface of the piezoelectric substrate. The IDT includes multiple fingers, each comprising a metal stack. The SAW filter further includes a cap layer on a surface of the IDT opposite the piezoelectric substrate and on areas of the surface of the piezoelectric substrate exposed by the IDT. The cap layer has a thickness in a range of and including 10 to 500 Angstroms and a high electrical resistivity (and thus a low electrical conductivity). For instance, in some embodiments, the electrical resistivity of the cap layer is greater than 10 kilo-ohm meters (K?·m). The SAW filter further includes an oxide overcoat layer on a surface of the cap layer opposite the IDT and the piezoelectric substrate.

Abstract: Embodiments described herein may provide a temperature-compensated surface acoustic wave (TCSAW) device, a method of fabricating a TCSAW device, and a system incorporating a TCSAW device. The TCSAW device may include a pyroelectric substrate, a plurality of electrodes formed on a first surface of the pyroelectric substrate, an amorphous silicon layer formed over the plurality of electrodes, and a temperature compensating layer formed over the amorphous silicon layer.

Abstract: Embodiments described herein may provide a temperature-compensated surface acoustic wave (TCSAW) device, a method of fabricating a TCSAW device, and a system incorporating a TCSAW device. The TCSAW device may include a pyroelectric substrate, a plurality of electrodes formed on a first surface of the pyroelectric substrate, an amorphous silicon layer formed over the plurality of electrodes, and a temperature compensating layer formed over the amorphous silicon layer.

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract: Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

Abstract: The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Abstract: A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the process include the formation of integrated circuit structures and MEMS structures.

Abstract: An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Abstract: A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the process include the formation of integrated circuit structures and MEMS structures.

Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.