Patents by Inventor Daniel Chieng

Daniel Chieng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11133745
    Abstract: The present embodiments allow multiphase buck controllers to be able to detect Power-on-Reset (POR) automatically and subsequently reboot the system and reconfigure the system as a single or multi-rail system. Some embodiments use an onboard bus that can communicate between controllers. In these and other embodiments, the system is able to recover automatically from a power failure afflicting any or all of the controllers. Embodiments are applicable to flexible plug-and-play modular digital buck regulation applications.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 28, 2021
    Assignee: Renesas Electronics America Inc.
    Inventors: Daniel Chieng, Michael Payne, David Beck, Adam Vaughn
  • Publication number: 20200274449
    Abstract: The present embodiments allow multiphase buck controllers to be able to detect Power-on-Reset (POR) automatically and subsequently reboot the system and reconfigure the system as a single or multi-rail system. Some embodiments use an onboard bus that can communicate between controllers. In these and other embodiments, the system is able to recover automatically from a power failure afflicting any or all of the controllers. Embodiments are applicable to flexible plug-and-play modular digital buck regulation applications.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 27, 2020
    Applicant: Renesas Electronics America Inc.
    Inventors: Daniel Chieng, Michael Payne, David Beck, Adam Vaughn
  • Patent number: 10700606
    Abstract: On embodiment pertains to an apparatus including a control loop configured to receive an output voltage sense signal. The control loop includes a compensator; a PWM signal generator coupled to an output of the compensator; a reference circuit configured to receive a tracking signal, and which is configured to low bandwidth low pass filter the tracking signal when the tracking signal amplitude becomes substantially constant and representative of an output voltage that is substantially non-zero, and an error amplifier having a first input coupled to an output of the reference circuit, a second input configured to receive the output voltage sense signal, and an output coupled to the compensator.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 30, 2020
    Assignee: Intersil Americas LLC
    Inventor: Daniel Chieng
  • Publication number: 20190058400
    Abstract: On embodiment pertains to an apparatus including a control loop configured to receive an output voltage sense signal. The control loop includes a compensator; a PWM signal generator coupled to an output of the compensator; a reference circuit configured to receive a tracking signal, and which is configured to low bandwidth low pass filter the tracking signal when the tracking signal amplitude becomes substantially constant and representative of an output voltage that is substantially non-zero, and an error amplifier having a first input coupled to an output of the reference circuit, a second input configured to receive the output voltage sense signal, and an output coupled to the compensator.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventor: Daniel CHIENG
  • Patent number: 10110127
    Abstract: On embodiment pertains to an apparatus including a control loop configured to receive an output voltage sense signal. The control loop includes a compensator; a PWM signal generator coupled to an output of the compensator; a reference circuit configured to receive a tracking signal, and which is configured to low bandwidth low pass filter the tracking signal when the tracking signal amplitude becomes substantially constant and representative of an output voltage that is substantially non-zero; and an error amplifier having a first input coupled to an output of the reference circuit, a second input configured to receive the output voltage sense signal, and an output coupled to the compensator.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: October 23, 2018
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Daniel Chieng
  • Publication number: 20170163155
    Abstract: On embodiment pertains to an apparatus including a control loop configured to receive an output voltage sense signal. The control loop includes a compensator; a PWM signal generator coupled to an output of the compensator; a reference circuit configured to receive a tracking signal, and which is configured to low bandwidth low pass filter the tracking signal when the tracking signal amplitude becomes substantially constant and representative of an output voltage that is substantially non-zero; and an error amplifier having a first input coupled to an output of the reference circuit, a second input configured to receive the output voltage sense signal, and an output coupled to the compensator.
    Type: Application
    Filed: April 20, 2016
    Publication date: June 8, 2017
    Inventor: Daniel Chieng
  • Patent number: 8494180
    Abstract: Systems and methods provided herein decrease an idle channel noise floor and reduce power during an idle channel input for low power audio devices that include a digital pulse width modulation (PWM) amplifier having a noise shaper. An audio data signal is monitored for an idle channel condition. The noise shaper performs quantization of the audio data signal and uses noise shaper filter coefficients to shape noise resulting from the quantization. Predetermined values for the noise shaper filter coefficients are used to shape the noise resulting from quantization while the idle channel condition is not being detected. The values of the noise shaper filter coefficients are reduced so that the values move toward zeros, and the reduced values of the noise shaper filter coefficients are used to attenuate noise resulting from quantization, while the idle channel condition is being detected.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: July 23, 2013
    Assignee: Intersil Americas Inc.
    Inventors: Travis John Guthrie, Daniel Chieng
  • Publication number: 20110170709
    Abstract: Systems and methods provided herein decrease an idle channel noise floor and reduce power during an idle channel input for low power audio devices that include a digital pulse width modulation (PWM) amplifier having a noise shaper. An audio data signal is monitored for an idle channel condition. The noise shaper performs quantization of the audio data signal and uses noise shaper filter coefficients to shape noise resulting from the quantization. Predetermined values for the noise shaper filter coefficients are used to shape the noise resulting from quantization while the idle channel condition is not being detected. The values of the noise shaper filter coefficients are reduced so that the values move toward zeros, and the reduced values of the noise shaper filter coefficients are used to attenuate noise resulting from quantization, while the idle channel condition is being detected.
    Type: Application
    Filed: August 18, 2010
    Publication date: July 14, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Travis Guthrie, Daniel Chieng
  • Publication number: 20070182486
    Abstract: Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.
    Type: Application
    Filed: January 26, 2006
    Publication date: August 9, 2007
    Inventors: Daniel Chieng, Michael Kost, Jack Andersen, Larry Hand
  • Publication number: 20070152750
    Abstract: Systems and methods for performance improvements in digital switching amplifiers using simulation-based feedback. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a simulator configured to model processing of audio signals by the plant. The outputs of the plant and the simulator are provided to a subtractor, the output of which is then added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal for input to the subtractor. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Jack Andersen, Peter Craven, Michael Kost, Daniel Chieng, Larry Hand, Wilson Taylor