Abstract: Testing a computer program comprises identification of resource access requests by the computer program to a resource provided by an underlying host. The resource access requests may be intercepted and a determined response may be returned instead of the actual response of the underlying host. In some exemplary embodiments, the resource may a clock of the underlying host and the response may be the time of the clock. In some exemplary embodiments, the computer program may be tested to check for validity during execution on a cloud computing environment, in which access to resources may yield results that on a non-cloud computing environments are generally not expectable. The testing may be performed on a non-cloud computing environments and simulate scenarios applicable to cloud computing environments.

Abstract: A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel operations on vector registers. Once loaded with data, an LU is read using a single port. The VGB initiates prefetch events that keep it full in response to the demand created by ‘gather’ instructions. The VGB includes one or more write ports for receiving data from the memory hierarchy and a read port capable of reading data from the columns of the LU to be loaded into a vector register. Data is extracted from the VGB by (1) using a separate port for each item read, (2) implementing each VGB entry as a shift register and shifting an appropriate amount until all entries are aligned, or (3) enforcing a uniform offset for all items.

Abstract: A method and apparatus for testing a computer program for correct execution by various computerized apparatuses, the method comprising: obtaining at least two configurations for a computing platform; for each configurations of the at least two configurations: setting the computing platform in accordance with the configuration; and executing a computer program on the computing platform using the configuration, thereby testing the computer program for correct execution by various computerized apparatuses.

Abstract: Systems and methods for cache optimization are provided. The method comprises tracing objects instantiated during execution of a program code under test according to type of access by one or more threads running in parallel, wherein said tracing provides information about order in which different instances of one or more objects are accessed by said one or more threads and whether the type of access is a read operation or a write operation; and utilizing tracing information to build a temporal relationship graph (TRG) for the accessed objects, wherein the objects are represented by nodes in the TRG and at least two types of edges for connecting the nodes are defined.

Abstract: A data transmission optimization method and system. The method comprises analyzing program code to identify data access calls in the program code, using one or more processor; determining whether a first data access call is for retrieving target data stored in a data structure with a plurality of fields, wherein the target data is stored in one or more target fields of the data structure; determining whether servicing the first data access call will result in transfer of non-target data stored in one or more non-target fields in the data structure; and replacing the first data access call with a second data access call, wherein servicing the second data access call will result in transfer of the target data and minimizes the transfer of non-target data.

Abstract: A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel operations on vector registers. Once loaded with data, an LU is read using a single port. The VGB initiates prefetch events that keep it full in response to the demand created by ‘gather’ instructions. The VGB includes one or more write ports for receiving data from the memory hierarchy and a read port capable of reading data from the columns of the LU to be loaded into a vector register. Data is extracted from the VGB by (1) using a separate port for each item read, (2) implementing each VGB entry as a shift register and shifting an appropriate amount until all entries are aligned, or (3) enforcing a uniform offset for all items.

Abstract: Testing a computer program comprises identification of resource access requests by the computer program to a resource provided by an underlying host. The resource access requests may be intercepted and a determined response may be returned instead of the actual response of the underlying host. In some exemplary embodiments, the resource may a clock of the underlying host and the response may be the time of the clock. In some exemplary embodiments, the computer program may be tested to check for validity during execution on a cloud computing environment, in which access to resources may yield results that on a non-cloud computing environments are generally not expectable. The testing may be performed on a non-cloud computing environments and simulate scenarios applicable to cloud computing environments.

Abstract: A novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for all installations of a software application, not just software in development mode or at a specific installation. Code coverage bits are implemented in either the instruction set architecture (ISA) of the central processing unit, the executable file of a software application, a companion file to the executable file or a code coverage table residing in memory of the computer system.

Abstract: Systems and methods for cache optimization are provided. The method comprises tracing objects instantiated during execution of a program code under test according to type of access by one or more threads running in parallel, wherein said tracing provides information about order in which different instances of one or more objects are accessed by said one or more threads and whether the type of access is a read operation or a write operation; and utilizing tracing information to build a temporal relationship graph (TRG) for the accessed objects, wherein the objects are represented by nodes in the TRG and at least two types of edges for connecting the nodes are defined.

Abstract: A method for optimizing program code is provided. The method comprises receiving a request to execute a computer program on a computer system; loading executable code generated for the computer program into memory; optimizing the executable code during the loading; and executing the optimized executable code. The executable code is optimized according to information collected about the computer system, and the optimized executable code and the collected information are stored for use during future optimization of the executable code.

Abstract: A method for transferring data from a general purpose register to a vector register, the method including splatting a byte of data directly from a general purpose register (GPR) to a vector register (VR) by means of vector permute instructions, and splatting another byte of data from the GPR to the VR and vectorially combining the data in the VR.

Abstract: A method and system for relative multiple-target branch instruction execution in a processor is provided. One implementation involves receiving an instruction for execution; determining a next instruction to execute based on multiple condition bits or outcomes of a comparison by the current instruction; obtaining a specified instruction offset in the current instruction; and using the offset as the basis for multiple instruction targets based on said outcomes, wherein the number of conditional branches is reduced.

Abstract: A novel and useful mechanism enabling the partitioning of a normally shared L1 data cache into several different independent caches, wherein each cache is dedicated to a specific data type. To further optimize performance each individual L1 data cache is placed in relative close physical proximity to its associated register files and functional unit. By implementing separate independent L1 data caches, the content based data cache mechanism of the present invention increases the total size of the L1 data cache without increasing the time necessary to access data in the cache. Data compression and bus compaction techniques that are specific to a certain format can be applied each individual cache with greater efficiency since the data in each cache is of a uniform type.

Abstract: a novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for all installations of a software application, not just software in development mode or at a specific installation. Code coverage bits are implemented in either the instruction set architecture (ISA) of the central processing unit, the executable file of a software application, a companion file to the executable file or a code coverage table residing in memory of the computer system.

Abstract: A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of a PowerPC Instruction Set Architecture (ISA), the step of combining including splatting a low nibble from the GPR into a low nibble in each element of a first VR by executing two “load vector for shift left” (lvsl) or “load vector for shift right” (lvsr) and one “vector subtract unsigned byte modulo” (vsububm), shifting a high nibble of the GPR into a low nibble the GPR, splatting the low nibble of the GPR into a low nibble in each element of a second VR by re-executing the two lvsl or lvsr and one vsububm instructions, shifting the low nibble of the second VR into a high nibble of the second VR and combining both first and second VRs into one VR.

Abstract: A system and corresponding methods that facilitate implementing and decoding variable size instruction fields in a fixed size instruction are provided. In accordance with one aspect of the invention, an instruction has one or more instructions fields, wherein each field is represented by a plurality of bits arranged in a first order. The decoding method comprises fetching the instruction into an instruction register; and determining a mapping foFr a plurality of bits that represent each instruction field, wherein according to the mapping a first set of bits represents a first instruction field, and a second set of bits represents a second instruction field; such that one or more bits in the first set overlap one or more bits in the second set.

Abstract: Systems and methods for prefetching data in a microprocessor environment are provided. The method comprises decoding a first instruction; determining if the first instruction comprises both a load instruction and embedded prefetch data; processing the load instruction; and processing the prefetch data, in response to determining that the first instruction comprises the prefetch data, wherein processing the prefetch data comprises determining a prefetch multiple, a prefetch address and the number of elements to prefetch, based on the prefetch data.

Abstract: An integrated circuit device includes a processing component and a cache, which is arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having an address length of ml bits. First and second buses are coupled between the processing component and the cache, the buses having bus widths of n1 and n2 bits, respectively, such that n1<m1. The processing component and the cache each include a respective address bus expander coupled to the first bus in order to compact at least some of the memory addresses for transmission over the first bus so that each of the at least some memory addresses is transmitted over the first bus in one cycle of the first bus.

Abstract: A method for transferring data from a general purpose register to a vector register, the method including splatting a byte of data directly from a general purpose register (GPR) to a vector register (VR) by means of vector permute instructions, and splatting another byte of data from the GPR to the VR and vectorially combining the data in the VR.

Abstract: A taxonomy for annotations found in program code. The taxonomy includes a set of meta-annotations associated with an annotation definition and a set of values for each meta-annotation. The meta-annotations describes properties of each annotation. The values describe one quality of its associated meta-annotation. The taxonomy is used in a method for instrumenting a piece of code. The method includes reviewing meta-annotations attached to each annotation definition within the piece of code to determine how to proceed with instrumenting the piece of code.