Patents by Inventor Daniel Claire Baker

Daniel Claire Baker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer, a chemical-mechanical alignment mark, and an apparatus for improving alignment for metal masking in conjunction with oxide and tungsten CMP
    Patent number: 6274940
    Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: August 14, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Daniel Claire Baker, Charles Franklin Drill, Milind Ganesh Weling
  • Apparatus for improving alignment for metal masking
    Publication number: 20010012674
    Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 9, 2001
    Inventors: Daniel Claire Baker, Charles Franklin Drill, Milind Ganesh Weling
  • Method and apparatus for improving alignment for metal masking in conjuction with oxide and tungsten CMP
    Patent number: 5952241
    Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: September 14, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Daniel Claire Baker, Charles Franklin Drill, Milind Ganesh Weling