Patents by Inventor Daniel Connelly
Daniel Connelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11664427Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.Type: GrantFiled: May 23, 2022Date of Patent: May 30, 2023Assignee: ATOMERA INCORPORATEDInventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
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Publication number: 20220285498Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
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Patent number: 11387325Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.Type: GrantFiled: November 23, 2020Date of Patent: July 12, 2022Assignee: ATOMERA INCORPORATEDInventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
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Publication number: 20210074814Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
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Method for making a semiconductor device including enhanced contact structures having a superlattice
Patent number: 10879356Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.Type: GrantFiled: March 8, 2019Date of Patent: December 29, 2020Assignee: ATOMERA INCORPORATEDInventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann -
Patent number: 10854717Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.Type: GrantFiled: November 16, 2018Date of Patent: December 1, 2020Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Patent number: 10847618Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: GrantFiled: November 16, 2018Date of Patent: November 24, 2020Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Patent number: 10840337Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.Type: GrantFiled: November 16, 2018Date of Patent: November 17, 2020Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Patent number: 10840335Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: GrantFiled: November 16, 2018Date of Patent: November 17, 2020Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Patent number: 10840336Abstract: A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.Type: GrantFiled: November 16, 2018Date of Patent: November 17, 2020Assignee: ATOMERA INCORPORATEDInventors: Daniel Connelly, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
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Patent number: 10818755Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.Type: GrantFiled: November 16, 2018Date of Patent: October 27, 2020Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Patent number: 10777451Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.Type: GrantFiled: March 8, 2019Date of Patent: September 15, 2020Assignee: ATOMERA INCORPORATEDInventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J Mears, Erwin Trautmann
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Publication number: 20200161426Abstract: A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: DANIEL CONNELLY, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
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Publication number: 20200161428Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Publication number: 20200161425Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Publication number: 20200161429Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS
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Publication number: 20200161430Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
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Publication number: 20200161427Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS
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Patent number: 10621294Abstract: A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the velocity is ballistically limited. The model further takes into account the inertial effects on the velocity and/or charge flux associated with carriers. The model computes the mobility and hence the velocity of carriers in accordance with their positions in the channel both along the direction of the current flow as well as the direction perpendicular to the current flow.Type: GrantFiled: February 1, 2016Date of Patent: April 14, 2020Assignee: SYNOPSYS, INC.Inventor: Daniel Connelly
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Patent number: 10593761Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.Type: GrantFiled: November 16, 2018Date of Patent: March 17, 2020Assignee: ATOMERA INCORPORATEDInventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears