Abstract: A modular modulo 3 module is provided having a plurality of input terminals for receiving in parallel two bytes of numerical data, and a plurality of output terminals for outputting the modulo 3 residue of each byte of data individually and the modulo 3 residue of the sum of the input bytes. The modulo 3 module is implemented through a plurality of first type modules which combine logically the numerical data on individual pairs of inputs and feed in turn a logrithmic array of second type modules which combine logically to generate the modulo 3 outputs.

Abstract: A high speed parallel operation, multiplication circuit is provided having a multiplier multiplexor which may function in combination with a column compressor for providing a resultant product, wherein, preferably, the multiplier multiplexor has been implemented using a modified Booth's algorithm, and wherein the column compressor operates to process every column within the same propagation delay whereby every input may create an output in essentially the same propagation time, i.e., true parallel operation requiring preferably no more than an average column propagation delay time.

Abstract: In a network for transferring a source field in a source word into a destination field in a destination word two basic hardware sub-functions are utilized: rotation and mask vector generation. In the network the destination field of a destination word is masked. Concurrently in the network, a source word is rotated bringing the source field thereof into corresponding alignment with the masked destination field and all but the source field of the source word is masked. Subsequent logical combining of the masked destination word and the rotated and masked source word generates the desired field transference. In one embodiment the required masking operation is accomplished during a single pass of the destination and source words through the network. In an alternate embodiment using less masking hardware only half of the required masking is accomplished during each pass and two passes are required before the logical combining to achieve the desired field transference.