Abstract: A digital computer memory prefetches, or reads ahead, a next sequential, odd, address data word from a backing memory store containing all such odd address data words to a high speed buffer register simultaneously that the memory fetches the immediately preceding, even address data word from a backing memory store containing all such even address data words to that requestor-user, one of selective one(s) of a multiplicity of such requestor-users with which the memory communicates, which is addressably reading such even address data word. Selective one(s) of the requestor-users, which one(s) is (are) predominantly sequential in successive read addressings, does (do) enable such prefetching through a unique signal communicated to the memory. Remaining requestor-users do disable, via the alternative condition of the same signal, any prefetching; causing thereby no disturbance to the priorly read-ahead, odd address, data word.