Abstract: The present invention provides a method and an apparatus that are utilized to enable the range of trace lengths of the bus of a mounting surface, such as a PCB, for example, to be maximized without violating setup and/or hold times. The method of the present invention utilizes information relating to certain timing parameters of the ICs and the package delays of the ICs to maximize the range of trace lengths of the PCB bus as a function of a selected clock offset. A clock offset is inserted into the global clock of the PCB bus and minimum and maximum PCB bus trace lengths are calculated as a function of the clock offset, The apparatus of the present invention is a computer that performs the calculations needed to perform the method of the present invention. For example, the computer receives the information relating to the timing parameters and the package delays of the ICs and processes the information to determine the minimum and maximum trace lengths for each signal of the ICs.

Abstract: A method for detecting bus fights in a simulated bus system comprising simulating a first logic sequence and a second logic sequence respectively representing an output sequence of a first simulated device and a second simulated drive to a simulated bus, and determining a bus fight condition exists when a high logic state of the first logic sequence and the second logic sequence is detected on an adjacent clock cycle is provided. A computer executable program operable to cause a computer to simulate a respective sequence of logic states of a first device and a second device, determine the first device has gained access to the bus during a first clock cycle, analyze the logic state of the second device, and determine a bus fight condition exists when the second device has gained access to the bus during a clock cycle adjacent to the first clock cycle is provided.

Abstract: The present invention provides a method and apparatus for selecting trace lengths for a bus of a mounting surface, such as, for example, a printed circuit board (PCB), and for selecting the relative locations of two or three ICs on the mounting surface, which will be referred to hereinafter as a PCB. The method of the present invention utilizes information relating to the trace lengths of the buses of the ICs at issue and certain timing parameters of the ICs to determine optimal trace lengths for the PCB bus and the appropriate relative locations for the ICs on the PCB. An offset is then inserted into the global clock of the PCB bus to optimize the setup margins of the ICs. Optimization of the setup margins maximizes the speed of the PCB bus. The apparatus of the present invention is a computer that performs the method of the present invention.