Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfill the requirements specified in the matching strategy.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: A method and system for increasing performance when modeling random latch values are provided. The system including a power management logic that provides a power signal (VDD) that includes a high portion and a low portion, a transformation logic that receives the VDD from the power management logic, generates a updated signal (VDD2) based on the VDD, and outputs the updated signal (VDD2), wherein the VDD2 includes a low portion that extends one cycle, and a latch connected to transformation logic, wherein the latch receives VDD2.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfil the requirements specified in the matching strategy.