Patents by Inventor Daniel Daeik Kim
Daniel Daeik Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817239Abstract: A vertical inductor structure includes a first laminate substrate forming a first portion of the vertical inductor structure and a second laminate substrate forming a second portion. Each laminate substrate includes a plurality of first traces embedded in a layer of the laminate substrate, a plurality of first vertical columns, and a plurality of second vertical columns. Each first vertical columns is coupled to a first end of a respective first trace, and each second vertical column is coupled to a second end of a respective first trace. The second laminate substrate is mounted on the first laminate substrate such that each first vertical column of the first laminate substrate is coupled to a respective first vertical column of the second laminate substrate, and each second vertical column of the first laminate substrate is coupled to a respective second vertical column of the second laminate substrate.Type: GrantFiled: December 5, 2018Date of Patent: November 14, 2023Assignee: QUALCOMM INCORPORATEDInventors: Daniel Daeik Kim, Bonhoon Koo, Babak Nejati
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Publication number: 20230352423Abstract: Disclosed is a device that includes a die and a protection layer surrounding the die. The protection layer is applied at a backend process prior to dicing a wafer to individual dies. The protection layer protects the die from chips and cracks during and after dicing the wafer.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Inventors: Sameer Sunil VADHAVKAR, Changhan Hobie YUN, Paragkumar Ajaybhai THADESAR, Nosun PARK, Daniel Daeik KIM
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Patent number: 11770115Abstract: An exemplary tunable circuit includes an inductor coupled to a node and a first capacitor coupled to the node. The tunable circuit also includes a variable capacitor coupled to the node, such that a total capacitance of the tunable circuit depends on a fixed capacitance of the first capacitor and a variable capacitance of the variable capacitor. In an example, the inductor and the first capacitor are both included in a passive device and the variable capacitor is in a semiconductor device. The variable capacitor allows the total capacitance to be modified for the purpose of, for example, calibrating the capacitance to account for manufacturing variations, and/or adjusting to a frequency range of operation used by wireless devices in a region of the world. The first capacitor may be a higher quality capacitor providing a larger portion of the total capacitance than the variable capacitor.Type: GrantFiled: April 20, 2021Date of Patent: September 26, 2023Assignee: QUALCOMM INCORPORATEDInventors: Changhan Hobie Yun, Hannu Laurila, Ville Lehtisalo, Ville Herman Brunou, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Wei Cheng
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Patent number: 11728293Abstract: Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies can be blocked or filtered out by, for example, a lumped-element circuit or a lumped-element filter consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device, or integrated passive device, is one example of a lumped-element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted on (i.e., coupled to) a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of hand-held mobile devices drives a need for reducing the sizes of chip modules that are inside a mobile device.Type: GrantFiled: February 3, 2021Date of Patent: August 15, 2023Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Sameer Sunil Vadhavkar
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Publication number: 20230230910Abstract: A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.Type: ApplicationFiled: January 19, 2022Publication date: July 20, 2023Inventors: Changhan Hobie YUN, Nosun PARK, Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR
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Publication number: 20230187340Abstract: An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.Type: ApplicationFiled: December 9, 2021Publication date: June 15, 2023Inventors: Nosun PARK, Changhan Hobie YUN, Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR
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Patent number: 11658403Abstract: A substrate that includes at least one dielectric layer, a plurality of interconnects, and a curved antenna coupled to a surface of the substrate. The curved antenna is curved relative to the surface of the substrate such that at least part of the curved antenna is offset from the surface of the substrate. The substrate includes a first antenna dielectric layer coupled to the surface of the substrate, an antenna ground interconnect coupled to the first antenna dielectric layer, and a second antenna dielectric layer coupled to the antenna ground interconnect. The antenna ground interconnect configured to be coupled to ground. The curved antenna is coupled to the second antenna dielectric layer.Type: GrantFiled: August 25, 2020Date of Patent: May 23, 2023Assignee: QUALCOMM INCORPORATEDInventors: Changhan Hobie Yun, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Sameer Sunil Vadhavkar
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Publication number: 20230082743Abstract: Disclosed are a device and techniques for fabricating the device. The device may include a top substrate including a plurality of top vias coupled to a first top metal layer that forms a top winding portion of a first inductor. The device also includes a middle substrate including one or more middle metal layers. The top substrate is disposed on the middle substrate. The one or more middle metal layers form a middle winding portion of the first inductor. The device also includes a bottom substrate electrically coupled to the middle substrate opposite the top substrate, where a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Inventors: Changhan Hobie YUN, Nosun PARK, Paragkumar Ajaybhai THADESAR, Daniel Daeik KIM, Sameer Sunil VADHAVKAR, Vinay PRAKASH
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Patent number: 11515247Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.Type: GrantFiled: January 14, 2021Date of Patent: November 29, 2022Assignee: QUALCOMM IncorporatedInventors: Nosun Park, Changhan Hobie Yun, Daniel Daeik Kim, Sameer Sunil Vadhavkar, Paragkumar Ajaybhai Thadesar
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Patent number: 11502652Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.Type: GrantFiled: May 8, 2020Date of Patent: November 15, 2022Assignee: QUALCOMM IncorporatedInventors: Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Changhan Hobie Yun, Sameer Sunil Vadhavkar, Nosun Park
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Publication number: 20220246552Abstract: Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies can be blocked or filtered out by, for example, a lumped-element circuit or a lumped-element filter consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device, or integrated passive device, is one example of a lumped-element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted on (i.e., coupled to) a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of hand-held mobile devices drives a need for reducing the sizes of chip modules that are inside a mobile device.Type: ApplicationFiled: February 3, 2021Publication date: August 4, 2022Inventors: Changhan Hobie Yun, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Sameer Sunil Vadhavkar
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Publication number: 20220248541Abstract: Certain aspects of the present disclosure generally relate to an electronic device. One example electronic device generally includes a SIP module having a circuit board and one or more electronic elements disposed above the circuit board, and one or more first connector contacts coupled to a bottom surface of the circuit board, the one or more first connector contacts being configured to electrically couple the circuit board to a connector receptacle.Type: ApplicationFiled: February 1, 2021Publication date: August 4, 2022Inventors: Daniel Daeik KIM, Changhan Hobie YUN, Paragkumar Ajaybhai THADESAR, Nosun PARK, Sameer Sunil VADHAVKAR
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Publication number: 20220223516Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.Type: ApplicationFiled: January 14, 2021Publication date: July 14, 2022Inventors: Nosun PARK, Changhan Hobie YUN, Daniel Daeik KIM, Sameer Sunil VADHAVKAR, Paragkumar Ajaybhai THADESAR
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Patent number: 11380471Abstract: A spiral inductor includes a spiral trace and a plurality of first projections extending along a first edge of the spiral trace. The spiral inductor may further include a plurality of second projections extending along a second edge of the spiral trace, the second edge being opposite the first edge.Type: GrantFiled: July 13, 2018Date of Patent: July 5, 2022Assignee: QUALCOMM IncorporatedInventors: Daniel Daeik Kim, Bonhoon Koo, Babak Nejati
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Publication number: 20220123735Abstract: An exemplary tunable circuit includes an inductor coupled to a node and a first capacitor coupled to the node. The tunable circuit also includes a variable capacitor coupled to the node, such that a total capacitance of the tunable circuit depends on a fixed capacitance of the first capacitor and a variable capacitance of the variable capacitor. In an example, the inductor and the first capacitor are both included in a passive device and the variable capacitor is in a semiconductor device. The variable capacitor allows the total capacitance to be modified for the purpose of, for example, calibrating the capacitance to account for manufacturing variations, and/or adjusting to a frequency range of operation used by wireless devices in a region of the world. The first capacitor may be a higher quality capacitor providing a larger portion of the total capacitance than the variable capacitor.Type: ApplicationFiled: April 20, 2021Publication date: April 21, 2022Inventors: Changhan Hobie Yun, Hannu Laurila, Ville Lehtisalo, Ville Herman Brunou, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Wei Cheng
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Publication number: 20220069193Abstract: A package that includes an integrated device, an integrated passive device and a void. The integrated device is configured as a filter. The integrated device includes a substrate comprising a piezoelectric material, and at least one metal layer coupled to a first surface of the first substrate. The integrated passive device is coupled to the integrated device. The integrated passive device is configured as a cap for the integrated device. The void is located between the integrated device and the integrated passive device.Type: ApplicationFiled: August 27, 2020Publication date: March 3, 2022Inventors: Changhan Hobie YUN, Nosun PARK, Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR
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Publication number: 20220069453Abstract: A substrate that includes at least one dielectric layer, a plurality of interconnects, and a curved antenna coupled to a surface of the substrate. The curved antenna is curved relative to the surface of the substrate such that at least part of the curved antenna is offset from the surface of the substrate. The substrate includes a first antenna dielectric layer coupled to the surface of the substrate, an antenna ground interconnect coupled to the first antenna dielectric layer, and a second antenna dielectric layer coupled to the antenna ground interconnect. The antenna ground interconnect configured to be coupled to ground. The curved antenna is coupled to the second antenna dielectric layer.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Inventors: Changhan Hobie YUN, Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Nosun PARK, Sameer Sunil VADHAVKAR
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Patent number: 11239158Abstract: An integrated circuit (IC) package comprising a first die, including an active layer opposite a backside surface of the first die supporting a plurality of backside pads is provided. The IC package also incorporates a package substrate coupled to the active layer. The package pads on the package substrate correspond to the plurality of backside pads. A passive device comprising a plurality of wire bonds is coupled to the plurality of backside pads and the plurality of package pads. The passive device may also comprise a plurality of wire bonds coupled to the package pads by through silicon vias (TSVs). Multiple dies may be coupled with die-to-die wire bonds coupled to backside pads on each die.Type: GrantFiled: October 8, 2020Date of Patent: February 1, 2022Assignee: QUALCOMM IncorporatedInventors: Paragkumar Ajaybhai Thadesar, Changhan Hobie Yun, Sameer Sunil Vadhavkar, Daniel Daeik Kim, Francesco Carrara
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Publication number: 20210375732Abstract: Certain aspects of the present disclosure generally relate to a dielectric removal methodology and a metal patterning approach to allow partial embedding of electronic components (e.g., surface mount devices (SMDs)) in a substrate. By partially embedding relatively taller SMDs, the overall height of an electronic device may be reduced.Type: ApplicationFiled: June 2, 2020Publication date: December 2, 2021Inventors: Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR, Francesco CARRARA, Daniel Daeik KIM
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Publication number: 20210351750Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.Type: ApplicationFiled: May 8, 2020Publication date: November 11, 2021Inventors: Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Changhan Hobie YUN, Sameer Sunil VADHAVKAR, Nosun PARK