Abstract: A method for locating a substantially rectangular pattern, in any orientation, in a digitized image used in a document processing system operates by identifying all connected components within the image, discarding those that do not meet certain size criteria, and on the remaining connected components identifying eight compass-position extreme points, four of which may represent the corners of the rectangular pattern. The relationships among the extreme points are then analyzed to determine whether an expected diagonal length, expected height, and expected width of the pattern are all present within a selected tolerance.

Abstract: A method for locating a substantially rectangular pattern, in any orientation, in a digitized image used in a document processing system operates by identifying all connected components within the image, discarding those that do not meet certain size criteria, and on the remaining connected components identifying eight compass-position extreme points, four of which may represent the corners of the rectangular pattern. The relationships among the extreme points are then analyzed to determine whether an expected diagonal length, expected height, and expected width of the pattern are all present within a selected tolerance.

Abstract: A method and apparatus for classification of scanned symbols into equivalence classes as may be used for image data compression. The present invention performs run-length symbol extraction and classifies symbols based on both horizontal and vertical run length information. An equivalence class is represented by an exemplar. Feature-based classification criteria for matching an exemplar is defined by a corresponding exemplar template. The feature-based classification criteria all use quantities, which includes the stroke width of symbols, that can be readily computed from the run endpoints. Reducing the number of equivalence classes is achieved through a process called equivalence class consolidation. Equivalence class consolidation utilizes the symbol classifier to identify matched exemplars indicating equivalence classes which may be merged. For a consolidated equivalence class, the exemplar matching the most symbols is selected as the representative for the class.

Abstract: A method for compression and decompression of dithered images is disclosed. Logical units (tiles) of the binary representation are classified into equivalence classes which are then compressed. Each equivalence class represents tiles having similar gray levels (i.e. the same number of black pixels), but which may have different sequences of black and white pixels. Each equivalence class has associated with it a predefined set of rendering exemplars. Each of the exemplars has a similar gray level. Upon decompression, each instance of an equivalence class takes on the value of one of the rendering exemplars which is selected pseudo-randomly.

Abstract: The glyphs of self-clocking glyph codes are written on regular hexagonal or pseudo-hexagonal lattice-like patterns of centers to reduce the risk of interglyph interference during the read process while also enabling the glyphs to be packed more densely while maintaining a given center-to-center spacing between them.

Abstract: A method and apparatus for consolidation of equivalence classes of scanned symbols as may be used for image data compression. The present invention performs run-length symbol extraction and classifies symbols based on both horizontal and vertical run length information. An equivalence class is represented by an exemplar. Feature-based classification criteria for matching an exemplar is defined by a corresponding exemplar template. The feature-based classification criteria all use quantities that can be readily computed from the run endpoints. Reducing the number of equivalence classes is achieved through a process called equivalence class consolidation. Equivalence class consolidation utilizes the symbol classifier to identify matched exemplars indicating equivalence classes which may be merged. For a consolidated equivalence class, the exemplar matching the most symbols is selected as the representative for the class.

Abstract: A method and apparatus for classification of scanned symbol into equivalence classes as may be used for image data compression. The present invention performs run-length symbol extraction and classifies symbols based on both horizontal and vertical run length information. An equivalence class is represented by an exemplar. Feature-based classification criteria for matching an exemplar is defined by a corresponding exemplar template. The feature-based classification criteria all use quantities that can be readily computed from the run endpoints. Reducing the number of equivalence classes is achieved through a process called equivalence class consolidation. Equivalence class consolidation utilizes the symbol classifier to identify matched exemplars indicating equivalence classes which may be merged. For a consolidated equivalence class, the exemplar matching the most symbols is selected as the representative for the class.

Abstract: A simulator for simulating the attenuation characteristics of a length of coaxial cable in a cable television (CATV) network employs a diplex filter to separate the CATV signal and AC power into at least two separate signal paths. The AC power path has a resistance selected to simulate the DC loop resistance of the desire length of cable. The CATV signal path is in parallel with the AC power path, and has an attenuation selected to simulate the characteristics of the cable at CATV frequencies. In the preferred embodiment, the simulator is equipped with separate signal paths for the upstream and downstream CATV signals that have attenuations selected to simulate the characteristics of the cable within the frequency bands used for upstream and downstream CATV signals, respectively. The resistor in the AC power path has a sufficiently high power rating to handle realistic AC power levels.

Abstract: In brief, a method of reducing an M X N input binary image (M rows of N pixels each) by a factor of m vertically and n horizontally includes the steps of performing at least one logical operation between bits in consecutive groups of m adjacent rows to provide a resultant single row for each group of m rows, and performing at least one logical operation between bits in consecutive groups of n adjacent columns to provide a resultant single column for each groups of n columns. For certain types of reductions, the resulting reduced image will be the desired output image, while for other types, the resultant image will be one of a required plurality of intermediate images, which are then combined to provide the desired output image.

Abstract: A coprocessor includes processing units, control circuitry, and circuitry for connecting the coprocessor to a host processor. The connecting circuitry includes slave circuitry and master circuitry. The slave circuitry receives requests for coprocessor operations from the host processor's bus and provides signals to the control circuitry so that requested operations are performed. The master circuitry receives requests for data transfer operations from the control circuitry; the master circuitry requests host bus operations and also transfers data between the coprocessor and the host bus to perform requested data transfer operations. The control circuitry includes a control/status register and a control store. The slave circuitry can change data in the control/status register or transfer data from the control/status register to the host bus. The slave circuitry can also transfer data between the host bus and the control store.

Abstract: A mask operand can be obtained using a composite operand. A composite operand is an operand with plural multi-bit component data items. A logic operation can be performed on the mask operand and the composite operand to select a subset of components. The mask operand can have one value, such as ON, in bit positions aligned with the subset of components and another value, such as OFF, in all other bit positions. Other operations can then be performed on the selected components. A mask operand and its inverse can be used to merge two other operands, such as by selecting the maximum or minimum of each pair of aligned components in the operands. A mask operand can be obtained from flag bits at an end of each component in a composite operand, by selecting the flag bits and propagating them across the components. A mask operand can also be obtained from flag bits at the least significant bit position by an arithmetic operation.

Abstract: A processor for performing orthogonal rotations. The processor has a plurality of memory units; each memory unit being capable of being a source memory unit having source data, or a destination memory unit having destination data; and rotation circuitry for performing rotations by orthogonally transforming the source data into the destination data. The rotation circuitry has a plurality of parallel to serial units which provide a serial output data from parallel input data and a rotation buffer. There is also interconnecting circuitry for interconnecting any of the input connections of the parallel to serial units in the rotation circuitry with any of the data connections of the memory units, and for connecting the output connections of the rotation buffer in the rotation circuitry with any of the data connections of the memory units.

Abstract: A SIMD parallel processor includes two types of circuitry interconnecting its processing units: One kind interconnects the processing units into an array so that each processing unit can transfer data to an adjacent processing unit in the array and can receive data from an adjacent processing unit; the processing units can, for example, be interconnected in a one-dimensional array. Another kind of interconnecting circuitry includes bus circuitry to permit greater freedom in transferring data to and from processing units. Connected to the bus is a register, so that data can be transferred between processing units by first transferring data from one processing unit to the register and by then transferring data from the register to another processing unit. Or data stored in the register can be sent to a subset or to all of the processing units. Similarly, control circuitry can itself provide data on the bus for transfer to one, a subset, or all of the processing units.

Abstract: A parallel processor includes processing units, data transfer circuitry, subsampling/spreading circuitry, and control circuitry. The subsampling/spreading circuitry can receive an item of data defining an image segment and use it to obtain another item of data defining the same image segment with a different amount of data. For example, a subsampling transceiver can obtain less data, such as one-half or 1/N as much, and a spreading transceiver can obtain more data, such as twice or N times as much. The data transfer circuitry can connect the processing units to the subsampling/spreading circuitry so that data can be transferred from any processing unit to the subsampling/spreading circuitry and vice versa. The processing units can be grouped and the data transfer circuitry can include N buses, with one processing unit in each group connected to each bus. The data transfer circuitry can also include a common bus and a holding register on the common bus.

Abstract: A parallel processor includes processing units, edge crossing circuitry, data transfer circuitry, interconnecting circuitry, and control circuitry. The edge crossing circuitry can receive an item of data that includes plural bits and can bit serially provide the item of data. The data transfer circuitry connects the processing units to the edge crossing circuitry. The interconnecting circuitry interconnects the processing units and the edge crossing circuitry. The processing units can be interconnected in pairs to form an array. The interconnections could form an array-wide shift register. The edge crossing circuitry can be interconnected to transfer items of data bit serially to processing units at the edges of the array, and can include a shift register.

Abstract: Arithmetic operations are performed on composite operands that include plural component data items. The operations obtain valid results even though the operations would ordinarily produce inter-component signals, such as carry or borrow signals or a shifted bit, causing invalid results. For example, the component data items can be pixel values or other data relating to pixels in an image. Instructions on a storage medium can be accessed and executed by a processor to obtain valid results despite intercomponent signals. Or special circuitry, such as gating circuitry or a mask register, can be used to prevent inter-component signals. Components in composite operands can be separated by buffer bits that are cleared or set to ensure valid results. Values of components can be biased before an operation to obtain valid results.

Abstract: Binary outcome operations are performed on composite operands. A composite operand is an operand that includes plural multi-bit component data items. A binary outcome operation obtains, for each component, a flag bit that depends on the numerical value of the component. A binary outcome operation can be performed by performing an arithmetic operation in parallel on a composite operand in which each component includes more than one bit. The arithmetic operation can add a value, producing a carry signal if a component and the added value together exceed a maximum possible value. Or the arithmetic operation can subtract a value, producing a borrow signal if a component is less than the subtracted value. Also, if the arithmetic operation subtracts a value that is equal to the component, the resulting data item includes only zeros; an operation in parallel can then obtain a single flag bit that is a zero only if the resulting data item includes only zeros.

Abstract: An existing character, in a text defined in image form by data such as a two-dimensional array, is copied to add a new character to the text. The existing character is found by performing character recognition on a two-dimensional data array defining an image that includes part of the text, such as a page. The array can be obtained from a scanner. A word that is recognized as including characters of the type needed is tested to determine whether it can be divided into the correct number of characters. The word is divided by finding connected components in the part of the array in which the word was found during recognition. The connected components are grouped into sets, each set being likely to be a character. If the word can be correctly divided, character-size arrays for its characters are obtained and saved. One of the arrays for the character type of the new character is selected and used to produce an array for the word in which it is included.