Patents by Inventor Daniel Devers
Daniel Devers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122989Abstract: Provided herein are compositions, methods, and systems, comprising a programmable nucleic acid-guided nuclease and sequence-diverged donor sequences. The compositions and methods described herein facilitate editing of a targeted locus using a diverged sequence encoding for a functional protein product.Type: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Inventors: Beeke Wienert, Rajiv Sharma, Daniel Dever, Aishwarya Churi, Christopher Bandoro
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Patent number: 11943509Abstract: System and methods are described to determining a recommendation for a user based on changes in objects detected on a network-connected surface. The system receives, from the network-connected surface, a plurality of object identifiers for a plurality of physically inanimate objects of different types detected on the network-connected surface, wherein the object identifiers indicate a positioning of each object; determines, based on the object identifiers, a first arrangement of the plurality of physically inanimate objects; detects one or more changes in the plurality of object identifiers, wherein the one or more changes correspond to one or more changes in positioning from the first arrangement; in response to detecting the one or more changes, determines a second arrangement of the plurality of physically inanimate objects; and generates a content recommendation based on the second arrangement.Type: GrantFiled: March 29, 2023Date of Patent: March 26, 2024Assignee: Rovi Guides, Inc.Inventors: Sara Dever, Jennifer L Holloway, Daniel P. Rowan, Mark D. Thompson
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Publication number: 20230229595Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Inventors: Craig BARNER, David ASHER, Richard KESSLER, Bradley DOBBIE, Daniel DEVER, Thomas F. HUMMEL, Isam AKKAWI
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Patent number: 11620223Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: GrantFiled: August 12, 2021Date of Patent: April 4, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
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Publication number: 20230089784Abstract: Provided herein are compositions, methods, and systems, comprising a programmable nucleic acid-guided nuclease and sequence-diverged donor sequences. The compositions and methods described herein facilitate editing of a targeted locus using a diverged sequence encoding for a functional protein product.Type: ApplicationFiled: April 12, 2022Publication date: March 23, 2023Inventors: Beeke WIENERT, Rajiv SHARMA, Daniel DEVER, Aishwarya CHURI, Christopher BANDORO
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Publication number: 20220145286Abstract: Methods and compositions for monitoring a plurality of independent genomic modifications in cell lineages are provided.Type: ApplicationFiled: April 7, 2020Publication date: May 12, 2022Inventors: Daniel Dever, Rajiv Sharma, Matthew Porteus, Ravindra Majeti, Joab Camarena, Thomas Koehnke
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Patent number: 11327759Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.Type: GrantFiled: September 25, 2018Date of Patent: May 10, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: David Albert Carlson, Shubhendu Sekhar Mukherjee, Michael Bertone, David Asher, Daniel Dever, Bradley D. Dobbie, Thomas Hummel
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Publication number: 20210374057Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Inventors: Craig BARNER, David ASHER, Richard KESSLER, Bradley DOBBIE, Daniel DEVER, Thomas F. HUMMEL, Isam AKKAWI
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Patent number: 11119929Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: GrantFiled: January 31, 2019Date of Patent: September 14, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
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Publication number: 20200250088Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.Type: ApplicationFiled: January 31, 2019Publication date: August 6, 2020Inventors: Craig Barner, David Asher, Richard Kessler, Brad Dobbie, Daniel Dever, Tom Hummel, Isam Akkawi
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Publication number: 20200097292Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: David Albert Carlson, Shubhendu Sekhar MUKHERJEE, Michael BERTONE, David Asher, Daniel DEVER, Bradley D. DOBBIE, Tom HUMMEL
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Patent number: 9870328Abstract: Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.Type: GrantFiled: November 14, 2014Date of Patent: January 16, 2018Assignee: CAVIUM, INC.Inventors: Shubhendu Sekhar Mukherjee, David Asher, Bradley Dobbie, Thomas Hummel, Daniel Dever
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Patent number: 9665505Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.Type: GrantFiled: November 14, 2014Date of Patent: May 30, 2017Assignee: CAVIUM, INC.Inventors: Shubhendu Sekhar Mukherjee, David Asher, Bradley Dobbie, Thomas Hummel, Daniel Dever
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Publication number: 20160140061Abstract: Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Shubhendu Sekhar Mukherjee, David Asher, Brad Dobbie, Tom Hummel, Daniel Dever
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Publication number: 20160140060Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Shubhendu Sekhar Mukherjee, David Asher, Brad Dobbie, Tom Hummel, Daniel Dever
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Publication number: 20060277066Abstract: Methods for use in, e.g., in-patient care computing environment, for user-centric (e.g., in-patient-centric) selection of at least one menu item are provided. A method in accordance with one embodiment of the present invention may include receiving a plurality of menu item identifiers, each menu item identifier being associated with a different menu item, associating the menu item identifiers with an electronic record associated with an in-patient, displaying the menu item identifiers on at least one patient-viewable display device, and receiving a user selection of at least one of the menu item identifiers. If desired, the method may additionally include filtering the menu item identifiers based on at least one criterion derived from the electronic record to create a set of filtered menu item identifiers and displaying the set of filtered menu item identifiers on the patient-viewable display device rather than the plurality of menu item identifier.Type: ApplicationFiled: December 16, 2005Publication date: December 7, 2006Inventors: Jill Hungerford, Charles Brackett, Daniel Devers