Patents by Inventor Daniel Devoe

Daniel Devoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973205
    Abstract: An energy storage system includes an energy storage component. It further includes heat generating electronics. It further includes a fluid circulator that transfers fluid between the energy storage component and the heat generating electronics. The circulator is controlled to alternatively transfer fluid from the battery to the heat generating electronics or from the heat generating electronics to the energy storage component based at least in part on a thermal state of the energy storage system.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 30, 2024
    Assignee: Lunar Energy, Inc.
    Inventors: Bozhi Yang, Tanner Bruce DeVoe, Tahina Christine Felisca, Kevin Richard Fine, Mark Daniel Goldman, Mark Holveck, Erica Viola Lewis, Conrad Xavier Murphy, Ian Gregory Spearing
  • Publication number: 20240128594
    Abstract: A wiring harness for a battery and inverter system includes a main cable. It further includes an inverter connector configured to plug the main cable into an inverter module. It further includes a first spur of the main cable terminating in a first-type battery device connector. It further includes a second spur of the main cable terminating in a second type battery device connector.
    Type: Application
    Filed: May 8, 2023
    Publication date: April 18, 2024
    Inventors: Peter H.J. How, Tanner Bruce DeVoe, Mark Holveck, Anthony Sagneri, Christopher Breckenridge Todd, Randol Aikin, Mark Daniel Goldman, Conrad Xavier Murphy, Kevin Richard Fine, Brian M. Neil
  • Publication number: 20240106050
    Abstract: In various embodiments, an energy storage mounting system includes an inverter wall bracket mounted to a wall, wherein an inverter is coupled to the inverter wall bracket. The system includes a battery wall bracket to which a battery block is coupled. The battery wall bracket interfaces with an auxiliary bracket that is mounted to the wall, is vertically translatable relative to the auxiliary bracket, and is at least in part ground-supported. The battery block is electrically connected to the inverter.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Christopher McCarthy, Tahina Christine Felisca, Peter H. J. How, Scott A. Whitman, Eamon Briggs, Sanchita Sheth, Tanner Bruce DeVoe, Mark Daniel Goldman, Kevin Richard Fine
  • Patent number: 8289675
    Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: October 16, 2012
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Publication number: 20100053842
    Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.
    Type: Application
    Filed: November 11, 2009
    Publication date: March 4, 2010
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Patent number: 7633739
    Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 15, 2009
    Inventor: Daniel Devoe
  • Publication number: 20090034155
    Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.
    Type: Application
    Filed: October 6, 2008
    Publication date: February 5, 2009
    Inventor: Daniel Devoe
  • Publication number: 20080291602
    Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventor: Daniel Devoe
  • Patent number: 7307829
    Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: December 11, 2007
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Patent number: 7075776
    Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: July 11, 2006
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Patent number: 7035080
    Abstract: A substrate includes a single-layer capacitor and various external contacts. A first external contact provides a first electrical connection to the single-layer capacitor. A second external contact provides a second electrical connection to the single-layer capacitor. The first and third external contacts are electrically connectable to another electrical component, and internal metallization structures or vias of conductive material electrically connect the second contact and the third contact to facilitate the single-layer capacitor being connectable in a parallel circuit with the other electrical component.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: April 25, 2006
    Inventors: Lambert Devoe, Alan Devoe, Daniel Devoe
  • Patent number: 6970341
    Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: November 29, 2005
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Patent number: 6816356
    Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: November 9, 2004
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Patent number: 6753218
    Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: June 22, 2004
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe, Hung Trinh
  • Patent number: 6751082
    Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: June 15, 2004
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe, Hung Trinh
  • Publication number: 20040042156
    Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
    Type: Application
    Filed: April 14, 2003
    Publication date: March 4, 2004
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe
  • Patent number: 6690558
    Abstract: A high power resistor device and method for making a high power resistor device. A resistor is formed on a first end of a fired, ceramic chip with multiple internal conductor electrodes, and end terminations are then applied to both ends of the chip. A power resistor device having a high power rating is thus provided having buried conductor electrodes electrically connected to end terminations, where the connection at the first end is through the resistor to form a power resistor structured to dissipate heat efficiently. In an alternative method of the present invention, both ends of the chip may be dipped in resistor paste to form resistors on both ends of the chip. In yet another alternative method of the present invention, a conductor under-layer is formed under the resistor, such as by first dipping the end of the chip in a conductor paste and firing the chip.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: February 10, 2004
    Inventors: Alan Devoe, Daniel Devoe
  • Publication number: 20030161091
    Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 28, 2003
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe, Hung Trinh
  • Publication number: 20030161090
    Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 28, 2003
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe, Hung Trinh
  • Patent number: 6587327
    Abstract: A monolithic capacitor structure includes at least first and second plates internal to a dielectric body, the plates extending inward from opposed conductive contacts on surfaces of the body, and forming capacitor(s) therebetween. A third plate extends within said body, electrically floating relative to the exterior contacts, and forming a capacitor with the first and second plates, and further forming a capacitor with additional conductive structures connected to the conductive contacts on the body. The resulting array of combined series and parallel capacitors formed by the third plate, in conjunction with the capacitor(s) formed by the first and second plates, provides effective wideband performance in an integrated, cost-effective structure.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: July 1, 2003
    Inventors: Daniel Devoe, Alan Devoe, Lambert Devoe