Abstract: Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Abstract: Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: An adjustable game call device is provided. The bell has an inlet end and an outlet end to define a channel for the continuous passage of a column of air therethrough, the bell having an expanding cross-sectional area along at least a portion of the channel. The adjustable game call device has an adjustable caller assembly that includes a barrier member disposed within the bell and an adjustment member attached to the barrier member. The barrier member is movable in an axial direction within the bell by actuating the adjustment member to vary a distance of the barrier member from the bell inlet between two predetermined positions. Varying the distance of the barrier member from the bell inlet modifies the column of air traveling through the channel to change a characteristic of an animal sound created when the adjustable game call device is in use.

Abstract: Signal sampler embodiments are provided for processing input signals along signal paths in response to mode-command signals. They include a follower transistor with a control terminal and a current terminal that establish at least part of a signal path. They also include a switched-capacitor network that receives signals from the current terminal in response to a first mode-command signal and that couple a selected one of a set of reference signals to the current terminal in response to a second mode-command signal. During a second mode-command signal, a bias switch is arranged to bias off the follower transistor by coupling a bias signal to the control terminal that approximates the selected reference signal. Accordingly, the amplitude of the reference signals can be increased to facilitate an increased dynamic range of the input signals without biasing the follower transistor into breakdown.

Abstract: Data driver systems are provided that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports in signal conditioning systems (e.g., analog-to-digital converters). The systems effectively reduce pin count by sharing pins between different drivers and selectively configuring the drivers in driver and high output-impedance states.

Abstract: Differential sampler structures are provided that reduce signal distortion and current demand. The structures include first and second buffers that drive first and second capacitors and first and second switches. First and second current pumps are capacitively coupled and also cross coupled to the first and second capacitors relative to the coupling of the first and second buffers to these capacitors. As a result, signal distortion and current demand are both reduced.

Abstract: LVDS drivers and analog-to-digital (ADC) systems are provided which facilitate easy alteration (e.g., replacement of a selectable resistor Rsel) of differential current levels and differential voltages in response to altered loads. These drivers and systems maintain common-mode levels in the loads which are unaffected by alterations in the loads and their associated differential current and voltage levels.

Abstract: Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals Ssns.