Patents by Inventor Daniel Douriet
Daniel Douriet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8722536Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: GrantFiled: August 5, 2013Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Publication number: 20130316534Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: ApplicationFiled: August 5, 2013Publication date: November 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Patent number: 8586476Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: GrantFiled: September 2, 2010Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Patent number: 8055486Abstract: A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.Type: GrantFiled: August 6, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao Gia-Harvey Truong, Roger D. Weekly
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Patent number: 7920978Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.Type: GrantFiled: October 30, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
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Patent number: 7917870Abstract: A method, apparatus, and computer program product are disclosed for automatically enhancing a power distribution system (PDS) in a ceramic integrated circuit package. The package includes multiple layers. The entire package is divided into a three-dimensional grid that includes multiple different grid cells. Information is associated with each one of the cells. For each one of the cells, the information included in the cell describes characteristics of the physical location of that cell relative to the other cells in the three-dimensional package. The information also describes any via or trace that already passes through said that cell. Potential new via and/or trace locations are automatically located throughout all of the entire package utilizing the information.Type: GrantFiled: August 1, 2007Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventor: Daniel Douriet
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Patent number: 7863724Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: GrantFiled: February 12, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Publication number: 20100330797Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: ApplicationFiled: September 2, 2010Publication date: December 30, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Patent number: 7765504Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.Type: GrantFiled: July 27, 2007Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Roger D. Weekly
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Patent number: 7671273Abstract: The illustrative embodiments described herein provide an apparatus and method for facilitating signal transmission using differential transmission lines. The apparatus includes a first differential transmission line. The first differential transmission line includes a first plurality of conductors. The first plurality of conductors includes a set of conductors. The apparatus also includes a second differential transmission line. The second differential transmission line includes a second plurality of conductors. The second plurality of conductors includes a first conductor and a second conductor. A first noise produced by the first conductor on the set of conductors is balanced by a second noise produced by the second conductor on the set of conductors. The first differential transmission line and the second differential transmission line facilitate signal transmission.Type: GrantFiled: October 9, 2007Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm Brian O'Reilly, Roger Donell Weekly
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Patent number: 7614141Abstract: A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.Type: GrantFiled: February 16, 2006Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Roger D. Weekly
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Patent number: 7607028Abstract: A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.Type: GrantFiled: May 30, 2006Date of Patent: October 20, 2009Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
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Publication number: 20090200074Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: ApplicationFiled: February 12, 2008Publication date: August 13, 2009Applicant: International Business Machines CorporationInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Publication number: 20090091401Abstract: The illustrative embodiments described herein provide an apparatus and method for facilitating signal transmission using differential transmission lines. The apparatus includes a first differential transmission line. The first differential transmission line includes a first plurality of conductors. The first plurality of conductors includes a set of conductors. The apparatus also includes a second differential transmission line. The second differential transmission line includes a second plurality of conductors. The second plurality of conductors includes a first conductor and a second conductor. A first noise produced by the first conductor on the set of conductors is balanced by a second noise produced by the second conductor on the set of conductors. The first differential transmission line and the second differential transmission line facilitate signal transmission.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm Brian O'Reilly, Roger Donell Weekly
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Publication number: 20090048794Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.Type: ApplicationFiled: October 30, 2008Publication date: February 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
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Publication number: 20090031270Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.Type: ApplicationFiled: July 27, 2007Publication date: January 29, 2009Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Roger D. Weekly
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Patent number: 7469199Abstract: An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.Type: GrantFiled: April 6, 2006Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
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Patent number: 7467050Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.Type: GrantFiled: May 30, 2006Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
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Patent number: 7460986Abstract: A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.Type: GrantFiled: April 25, 2006Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao Gia-Harvey Truong, Roger D. Weekly
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Publication number: 20080294414Abstract: A computer program product is provided for power delivery analysis and design for a hierarchical system. The product includes a storage medium, readable by a processing circuit, for storing instructions for execution by the processing circuit for facilitating a method. The method includes building a model corresponding to each element of the hierarchical system, and compiling a repository that contains models corresponding to each element, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method also includes performing optimized gridding for each element, the net list, the domain list, the component list, the pin list, and the layer list; assembling a system model from the models contained in the repository; flattening the system model by converting the system model to a flattened system model that consists entirely of resistors; and running a simulation on the flattened system model.Type: ApplicationFiled: August 6, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao Gia-Harvey Truong, Roger D. Weekly