Abstract: A system includes a memory, an interface, and a processor. The memory stores a set of messages associated with a first user. The processor receives an indication of a conversation between the first user and at least a second user. In response, the processor selects a first message from the set of messages associated with the first user and uses the interface to present the first message to the second user as a suggestion to transmit to the first user. The processor determines that the second user transmitted the first message to the first user. In response to determining that the second user transmitted the first message to the first user, the processor updates the set of messages associated with the first user.

Abstract: A system includes a memory, an interface, and a processor. The memory stores a set of messages associated with a first user. The processor receives an indication of a conversation between the first user and at least a second user. In response, the processor selects a first message from the set of messages associated with the first user and uses the interface to present the first message to the second user as a suggestion to transmit to the first user. The processor determines that the second user transmitted the first message to the first user. In response to determining that the second user transmitted the first message to the first user, the processor updates the set of messages associated with the first user.

Abstract: A system includes a memory, an interface, and a processor. The memory stores a set of messages associated with a first user. The processor receives an indication of a conversation between the first user and at least a second user. In response, the processor selects a first message from the set of messages associated with the first user and uses the interface to present the first message to the second user as a suggestion to transmit to the first user. The processor determines that the second user transmitted the first message to the first user. In response to determining that the second user transmitted the first message to the first user, the processor updates the set of messages associated with the first user.

Abstract: The present invention relates to isolated Nato3 mutant polypeptides. Methods for stimulating a brain cell to differentiate into a dopaminergic progenitor neuronal cell or a dopaminergic neuron comprises increasing phosphorylation of Nato3 in the brain cells and culturing the brain cells until a progenitor dopaminergic neuronal cell marker or a dopaminergic neuronal cell marker is expressed in the cultured brain cells. Methods for treating Parkinson's disease (PD) in a subject comprises administering to the subject in need thereof, a composition comprising progenitor dopaminergic neuronal cells and/or dopaminergic neuronal cells expressing a Nato3 mutant polypeptide to the brain of the subject.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Provided is a device for monitoring printer-related data on USB cables. The USB-compatible device comprises a first USB connector, a second USB connector, a processor, and a non-volatile memory. The device stores printer-related data, reports stored printer-related data to a server, and removes the stored printer-related data from the non-volatile memory.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: The present invention relates to isolated Nato3 mutant polypeptides. Methods for stimulating a brain cell to differentiate into a dopaminergic progenitor neuronal cell or a dopaminergic neuron comprises increasing phosphorylation of Nato3 in the brain cells and culturing the brain cells until a progenitor dopaminergic neuronal cell marker or a dopaminergic neuronal cell marker is expressed in the cultured brain cells. Methods for treating Parkinson's disease (PD) in a subject comprises administering to the subject in need thereof, a composition comprising progenitor dopaminergic neuronal cells and/or dopaminergic neuronal cells expressing a Nato3 mutant polypeptide to the brain of the subject.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Methods and apparatuses for single level cell caching are described, According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: Structures and method for reducing junction leakage in semiconductor devices. The die can include a substrate having a cut edge, a first region of first conductivity type within the substrate and a region of a second conductivity type within the substrate and in contact with the first region forming a junction. At least one semiconductor device is on the substrate. A second region of the first conductivity type is between the plurality of semiconductor devices and the cut edge within the region of the second conductivity type, and extending to the junction. The second region of the first conductivity type can isolate the at least one semiconductor device from leakage pathways created by saw damage at the junction along the cut edge.

Abstract: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier.

Abstract: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier.

Abstract: A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier.

Abstract: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

Abstract: Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.