Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics. A secondary master central processing system is configured to couple the plurality of PCIe subfabrics.

Abstract: A status monitoring system includes a signal generation subsystem configured to receive a plurality of binary status signals from a plurality of monitored subcomponents and encode the plurality of binary status signals to generate a status signal indicative of the status of the plurality of monitored subcomponents. One or more processing subsystems are configured to receive the status signal and control a controlled subcomponent based, at least in part, upon the status signal.

Abstract: A signal generation subsystem is configured to receive a plurality of status signals from a plurality of monitored subcomponents within a system being monitored and generate a cumulatively-encoded status signal based, at least in part, upon the plurality of binary status signals, which is indicative of the overall health of the system being monitored.

Abstract: A user-configurable decoder circuit is associated with a controlled subcomponent and is configured to receive a cumulatively-encoded status signal and compare the cumulatively-encoded status signal to a user-definable threshold that defines a subcomponent policy for the controlled subcomponent.

Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit.

Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics including at least a first PCIe subfabric and a second PCIe subfabric. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit. The first PCIe subfabric is configured to enable multipath communication between a first element coupled to the first PCIe subfabric and a second element coupled to the second PCIe subfabric.

Abstract: An adapter assembly includes an adapter board. A first connector assembly is coupled to the adapter board and is configured to releasably electrically couple the adapter board to a high-availability IT component. A second connector assembly is coupled to the adapter board and is configured to releasably couple the adapter board to a non-hot-swappable industry standard expansion card. The adapter board includes hot swap logic configured to enable the non-hot-swappable industry standard expansion card to function as a hot-swappable industry standard expansion card.

Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. Each of the plurality of PCIe subfabrics includes a managing central processing unit and a PCIe fabric switch. One or more communication paths is configured to allow communication between the PCIe fabric switch included within each of the plurality of PCIe subfabrics.

Abstract: A signal generation circuit for producing an identification signal at a defined frequency. A frequency calibration circuit is electrically coupled to the signal generation circuit and is configured to set the defined frequency. The frequency calibration circuit includes a first calibration portion positioned on a first electrical subsystem and a second calibration portion positioned on a second electrical subsystem. An identification circuit is configured to process the identification signal to generate an identification result.

Abstract: An adapter assembly includes an adapter board. A first connector assembly is coupled to the adapter board and is configured to releasably electrically couple the adapter board to a high-availability IT component. A second connector assembly is coupled to the adapter board and is configured to releasably couple the adapter board to an industry standard expansion card. The adapter assembly is configured to be positioned within an enclosure of a hot swappable IT carrier assembly.

Abstract: An IO subsystem, for use with an IT computing device, includes a cage assembly configured to releasably engage a chassis of the IT computing device and to receive a plurality of IO adapter cards. A midplane adapter assembly, positioned within the cage assembly, includes a first electrical connector system configured to engage a generic connector system included within the IT computing device and a second electrical connector system configured to engage the plurality of IO adapter cards. A coupling system is configured to releasably couple the cage assembly to the chassis of the IT computing device.

Abstract: A status monitoring system includes a signal generation subsystem configured to provide a status signal indicative of the status of one or more monitored subcomponents. A processing subsystem is associated with a controlled subcomponent and is configured to: assign a subcomponent policy to the controlled subcomponent, receive the status signal, compare the status signal to the subcomponent policy, and effectuate a procedure on the controlled subcomponent based, at least in part, upon the comparison of the status signal and the subcomponent policy.

Abstract: A 1U rack-mountable computing device includes a storage component configured to include one or more storage devices. A second component is configured to be releasably coupleable to the storage component. A coupling system is configured to releasably couple the storage component to the second component.

Abstract: A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Abstract: A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Abstract: A system having: a midplane having air flow channels therein; a disk drive mounted to a first side of the midplane; and a temperature sensors mounted to the midplane. The system includes a pair of electrical chassis connected to a second side of the midplane. A first one of the chassis has therein: a fan; and a fan controller for controlling speed of the fan in response to a temperature control signal. A second one of the chassis has therein: a microprocessor for: detecting temperature signals produced by the temperature sensors; comparing differences between the detected temperature signals; and selecting one of the detected temperature control signal from the compared differences as the temperature control signal. A faulty one of the temperature sensors is detected by: selecting one of the detected temperature control signal as the faulty one of the plurality of temperature sensors from the compared differences.

Abstract: A data storage system includes a first and second boards disposed in a chassis. The first board has disposed thereon a first Serial Attached Small Computer Systems Interface (SAS) expander, a first management controller (MC) in communication with the first SAS expander, and management resources accessible to the first MC. The second board has disposed thereon a second SAS expander and a second MC. The system also has a communications link between the first and second MCs. Primary access to the management resources is provided in a first path which is through the first SAS expander and the first MC, and secondary access to the first management resources is provided in a second path which is through the second SAS expander and the second MC.

Abstract: A method of transmitting data includes synchronizing a system clock with a real time clock. Digital data is collected from multiple sources at a system clock time. A sample counter provides a count for each system clock time. The digital data for each source is associated with the count. A data cell is composed from the digital data associated with at least one count and a source identifier. A data frame is created from the data cells from every source. A cell frame is created from a plurality of data frames, and a time frame is composed from a plurality of cell frames. A heads-up cell including the count is transmitted before the time frame. A time/count cell including the count and the real time is transmitted with the associated time frame.

Abstract: A data storage system includes a first and second boards disposed in a chassis. The first board has disposed thereon a first Serial Attached Small Computer Systems Interface (SAS) expander, a first management controller (MC) in communication with the first SAS expander, and management resources accessible to the first MC. The second board has disposed thereon a second SAS expander and a second MC. The system also has a communications link between the first and second MCs. Primary access to the management resources is provided in a first path which is through the first SAS expander and the first MC, and secondary access to the first management resources is provided in a second path which is through the second SAS expander and the second MC.

Abstract: A system for providing television, information and data signals via a transmission network to selected subscribers, to groups of subscribers, or to all subscribers connected in common to the transmission network. An address code signal is stored at the subscriber station, and an option code signal is sent to the particular subscriber station from a head end of the network. Signals having an address portion designative of the option code or address code signal are sent down the transmission line and are translated by the subscriber station in the event the address matches the first and second code signal. Thus signals can be sent to all subscribers which have option codes designated by the address of data packets transmitted down the transmission line. These groups of subscribers can be all subscribers, individual smaller groups of subscribers, or a group consisting of even a single subscriber. The option codes can be changed from the head end at will.