Abstract: Embodiments described herein include a system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for delay-based physical unclonable functions (PUFs) for chiplets to verify system integrity. A die may include a plurality of chiplets including a first chiplet and a second chiplet. The first chiplet may be connected to the second chiplet via an interposer. As part of an authentication process, the first chiplet may request the second chiplet to transmit a signal via one or more wires of the interposer. A first signature based on the characteristics of the transmitted signal may be measured at a first time, which constitutes the first evaluation of the PUF. The first signature may be used as a baseline comparison for subsequent signatures as a means to confirm that the chiplets, interposers, and/or interconnects have not been altered or modified.

Abstract: A technique is presented for performing a physical unclonable function (PUF) using an array of SRAM cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation. An authentication challenge is issued to the array of SRAM cells by activating two or more wordlines concurrently. The response is simply the value that the SRAM produces from a read operation when the challenge condition is applied. The number of challenges that can be applied the array of SRAM cells grows exponentially with the number of SRAM rows and these challenges can be applied at any time without power cycling.

Abstract: A technique is presented for performing a physical unclonable function (PUF) using an array of SRAM cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation. An authentication challenge is issued to the array of SRAM cells by activating two or more wordlines concurrently. The response is simply the value that the SRAM produces from a read operation when the challenge condition is applied. The number of challenges that can be applied the array of SRAM cells grows exponentially with the number of SRAM rows and these challenges can be applied at any time without power cycling.

Abstract: A technique is presented for performing a physical unclonable function (PUF) using an array of SRAM cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation. An authentication challenge is issued to the array of SRAM cells by activating two or more wordlines concurrently. The response is simply the value that the SRAM produces from a read operation when the challenge condition is applied. The number of challenges that can be applied the array of SRAM cells grows exponentially with the number of SRAM rows and these challenges can be applied at any time without power cycling.

Abstract: A technique is presented for performing a physical unclonable function (PUF) using an array of SRAM cells. The technique can be viewed as an attempt to read multiple cells in a column at the same time, creating contention that is resolved according to process variation. An authentication challenge is issued to the array of SRAM cells by activating two or more wordlines concurrently. The response is simply the value that the SRAM produces from a read operation when the challenge condition is applied. The number of challenges that can be applied the array of SRAM cells grows exponentially with the number of SRAM rows and these challenges can be applied at any time without power cycling.

Abstract: The present disclosure provides a method and a system for characterizing and identifying an electronic device using a physical fingerprint. In one aspect, the characterizing method includes determining the physical fingerprint of a test device using selected memory cells of an SRAM array in the test device, and storing data associated with the physical fingerprint in a database. The physical fingerprint of the test device includes data retention voltages respectfully corresponding to the selected memory cells. In one aspect, the identifying method includes characterizing a test device using data retention voltages of selected memory cells in the test device as a physical fingerprint of the test device, and comparing the physical fingerprint of the test device with a predetermined fingerprint of a target device.

Abstract: A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.

Abstract: A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.