Abstract: Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.

Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Abstract: Methods and apparatus are disclosed for distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system. In one embodiment, a packet switching system detects faults and propagates indications of these faults to the input interfaces of a packet switch, so the packet switch can adapt the selection of a route over which to send a particular packet. Faults are identified by various components of the packet switching system and relayed to one or more switching components to generate a broadcast packet destined for all input ports (i.e., to each I/O interface in a packet switch having folded input and output interfaces). Other embodiments, generate one or more multicast or unicast packets. The I/O interface maintains one or more data structures indicating the state of various portions of the packet switching system.

Abstract: A multiprocessor system and method includes a processing sub-system having a plurality of processors and a processor memory system. A scalable network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces. Each I/O interface has a local cache and is operable to couple a peripheral device to the multiprocessor system and to store copies of data from the processor memory system in the local cache for use by the peripheral device. A coherence domain for the multiprocessor system includes the processors and processor memory system of the processing sub-system and the local caches of the I/O sub-system.

Abstract: According to the invention, methods and apparatus are disclosed for selecting one of multiple of paths between two points over which to route a data item based on the destination of the data item and the traffic between the two points over the multiple paths. A switching system can use the disclosed methods and apparatus to more efficiently distribute data packets among switching fabrics than currently accomplished by known techniques. In one implementation, distribution cycles have been established for sending data between two points, where each path between the endpoints is used a predetermined number of times (e.g., one, two) within each cycle. To economize the amount of traffic data collected, the multiple paths can be partitioned into subsets for which traffic data is maintained only for the current subset. Additionally, the distribution of traffic between the two points can be further partitioned into traffic of a particular type or priority between the two points.

Abstract: Methods and apparatus are disclosed for propagating timestamp floors throughout a packet switching system and using the timestamp floors received at a first component of the packet switching system to determine when a packet may be sent from a packet switching system. Each input of a first stage of a packet switching system maintains a floor register which is updated by copying the timestamp from each arriving packet. In some systems, if a packet is not received during a packet time, the timestamp is automatically updated, typically by adding a fixed time value. Periodically, the first stage switching element forwards a timestamp floor to the next stage switching elements. In one implementation, this distributed timestamp floor is the lesser of the earliest timestamp in one of the floor registers in the input queues, and the earliest timestamp in an output queue for the particular next stage switching element.

Abstract: In one implementation, a first set of packet switch sequence numbers is used for end-to-end resequencing of packets within a packet switch, and a second set of interconnection network sequence number is used in the resequencing of packets within an interconnection network of the packet switch. A packet switch sequence number is maintained at each input interface of the packet switch for each output interface, while each output interface maintains a packet switch sequence number for each input interface. A corresponding sequence number is added to packets sent between corresponding input-output interface pairs. Similarly, an interconnection network sequence number is maintained at each input port of an interconnection network for each output port, while each output port maintains an interconnection network sequence number for each input port. A corresponding sequence number is added to packets sent between corresponding input-output port pairs.

Abstract: Methods and apparatus are disclosed for accumulating and distributing information in a packet switching system. For example, it is desirable in certain packet switching systems to communicate the status of internal queues and other port status information from an individual port to all other ports (or at least those which are communicating with the individual port). The amount of information being sent from the individual port is typically very small, such as on the order of a few bits or bytes. By accumulating the information and then broadcasting the collected flow control information, a vast amount of switch fabric resources (e.g., bandwidth) can be saved. In one implementation, flow control information is sent to a destination (e.g., a “mailbox”) within a packet switching fabric which includes a memory in which flow control information is accumulated. After a period of time or based on the occurrence of some event, the accumulated flow control information is distributed.

Abstract: A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

Abstract: A system and method for partitioning to support high availability of a multiprocessor system. The system comprises a plurality of masters, including processors, input/output devices, or the like, and is divided into regions. Per-region access rights are assigned to the system resources. The regions are grouped into partitions, wherein a partition is a portion of the system that is treated as a single unit with respect to failure. Failure of a master in a given region only affects resources accessible to that given region. Per-region access can be to main memory on a per-page basis, for example. Alternatively, the per-region access can limit access to directory storage, input/output ports and devices, control or diagnostics registers.

Abstract: An input/output flow control system for a processor system having an input/output request source (e.g., a processor) and a plurality of input/output request targets (e.g., I/O busses) uses a NACKing (negatively acknowledging) scheme to prevent a common I/O path from becoming blocked due to the blockage of one or more I/O buses. The system includes a flow controller associated with each of the targets for receiving input/output requests from the source, for accepting (ACKing) a request if the intended target can accept the request, and for NACKing a request if the intended target cannot accept the request. The system also includes a processor or source interface for resending the NACKed requests to the intended target and for cooperating with the flow controller so that the NACKed requests are accepted by the flow controller in the proper order.

Abstract: A clock system for a distributed multiprocessor system includes a plurality of local clock circuits and a distribution network. The distribution network includes a plurality of interconnected routers. Each local clock circuit is associated with a processing node of the multiprocessor system. Each local clock circuit generates a global clock source signal, provides the global clock source signal to the distribution network, receives a global clock signal back from the distribution network, and generates a global time value based on a local clock signal and the global clock signal. The router is part of the distribution network of the multiprocessor system. The router receives the global clock source signals from each of the local clock circuits, selects one of the global clock source signals as the global clock signal and provides the global clock signal to the distribution network for distribution to each of the local clock circuits.

Abstract: A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

Abstract: A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.

Abstract: A system and method for transmitting data, using a source synchronous clocking scheme, over a communication (or data) link. A source synchronous driver (SSD) receives a micropacket of parallel data and serializes this data for transfer over the communication link. The serial data is transferred onto the communication link at a rate four times as fast as the parallel data is received by the SSD. A pair of source synchronous clocks are also transmitted across the communication link along with the serial data. The pair of clocks are the true complement of one another. A source synchronous receiver (SSR) receives the serial data and latches it into a first set of registers using the source synchronous clocks. The serial data is then latched into a second set of registers in parallel. The second set of registers are referred to as "ping-pong" registers. The ping-pong registers store the deserialized data.

Abstract: A page migration controller is described. The page migration controller determines whether a memory page addressed by a memory access request should be migrated from a local processing node to a requester processing node. The page migration controller accesses an array to obtain a first count associated with the addressed memory page and the requester processing node, and a second count associated with the addressed memory page and the local processing node. The first count is incremented, and then the second count is subtracted from the incremented first count to obtain a difference between the second count and the incremented first count. A comparator determines whether the difference is greater than a migration threshold value. If the difference is greater than the migration threshold value, then a migration interrupt is issued.

Abstract: A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion.