Patents by Inventor Daniel Elmhurst
Daniel Elmhurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8971126Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: GrantFiled: May 29, 2014Date of Patent: March 3, 2015Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Publication number: 20140293697Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: ApplicationFiled: May 29, 2014Publication date: October 2, 2014Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 8767476Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: GrantFiled: April 25, 2011Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 8391061Abstract: In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.Type: GrantFiled: December 21, 2009Date of Patent: March 5, 2013Assignee: Intel CorporationInventors: Daniel Elmhurst, Giovanni Santin, Michele Incarnati, Violante Moschiano, Ercole Diiorio
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Patent number: 8264882Abstract: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.Type: GrantFiled: December 7, 2011Date of Patent: September 11, 2012Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Giovanni Santin
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Publication number: 20120075932Abstract: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.Type: ApplicationFiled: December 7, 2011Publication date: March 29, 2012Inventors: Violante MOSCHIANO, Daniel Elmhurst, Giovanni Santin
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Patent number: 8085591Abstract: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.Type: GrantFiled: May 20, 2008Date of Patent: December 27, 2011Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Giovanni Santin
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Publication number: 20110199826Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: ApplicationFiled: April 25, 2011Publication date: August 18, 2011Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Patent number: 7969788Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: GrantFiled: August 21, 2007Date of Patent: June 28, 2011Assignee: Micron Technology, Inc.Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Publication number: 20100097856Abstract: In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.Type: ApplicationFiled: December 21, 2009Publication date: April 22, 2010Inventors: Daniel Elmhurst, Giovanni Santin, Michele Incarnati, Violante Moschiano, Ercole Diiorio
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Patent number: 7646108Abstract: Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.Type: GrantFiled: September 29, 2006Date of Patent: January 12, 2010Assignee: Intel CorporationInventors: Fabrice Paillet, Nick Triantafillou, Azam Barkatullah, Daniel Elmhurst, Peter Harrington, Raymond W. Zeng
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Publication number: 20090290426Abstract: In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.Type: ApplicationFiled: May 20, 2008Publication date: November 26, 2009Inventors: Violante Moschiano, Daniel Elmhurst, Giovanni Santin
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Patent number: 7539059Abstract: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.Type: GrantFiled: December 29, 2006Date of Patent: May 26, 2009Assignee: Intel CorporationInventors: June Lee, Daniel Elmhurst
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Patent number: 7535787Abstract: Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.Type: GrantFiled: June 6, 2007Date of Patent: May 19, 2009Inventors: Daniel Elmhurst, Violante Moschiano, Paul Ruby
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Publication number: 20090052269Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.Type: ApplicationFiled: August 21, 2007Publication date: February 26, 2009Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
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Publication number: 20080304327Abstract: Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.Type: ApplicationFiled: June 6, 2007Publication date: December 11, 2008Inventors: Daniel Elmhurst, Violante Moschiano, Paul Ruby
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Publication number: 20080159005Abstract: A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: June Lee, Daniel Elmhurst
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Publication number: 20080158986Abstract: In a method of operation, a flash memory cell is programmed, a word-line voltage is coupled to the flash memory cell, and a state of the flash memory cell is sensed at intervals to generate data to indicate a state of the flash memory cell. In a method of operation, a latch in a cache memory of a NAND flash memory is switched off, and the latch is initialized while the latch is switched off. A read voltage is coupled to a gate of a selected flash memory cell in the NAND flash memory where the selected flash memory cell is coupled to a bit-line, and the bit-line is coupled to an input of the latch while a voltage on the bit-line is changing.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Daniel Elmhurst, Giovanni Santin, Michele Incarnati, Violante Moschiano, Ercole Diiorio
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Publication number: 20080080103Abstract: Some embodiments include a die having an output control circuit to interact with an output circuit to convert a source voltage into at least one output voltage. The die may also have a converter circuit to convert the output voltage into at least one additional output voltage.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Fabrice Paillet, Nick Triantafillou, Azam Barkatullah, Daniel Elmhurst, Peter Harrington, Raymond W. Zeng
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Publication number: 20080008010Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: ApplicationFiled: December 28, 2006Publication date: January 10, 2008Inventors: Daniel Elmhurst, Karthikeyan Ramamurthi, Quan Ngo, Robert Melcher