Abstract: An ECL latch having a clock enable is provided with a first current source for the latch and a second current source for the clock enable. The latch alternates between a latch mode and a transparent mode under the control of a CLOCK signal. The clock enable operates to inhibit CLOCK signal control of the latch and holds the latch in the latch mode when an appropriate enable signal is applied to the clock enable. A current switch is provided to gate current from the second current source to the latch so that current from both current sources is gated to the latch during the transparent mode when the CLOCK signal controls latch operation. In this manner, the speed of operation of the latch during the transparent mode is increased. Thus, the latch will have an improved propagation delay to permit latch operation with a smaller clock period for a given supply current.

Abstract: A method and apparatus for providing an emitter coupled logic 2 to 1 multiplexer latch. The latch has a feedback loop for latching data within the loop and at least two data ports for transmitting data. A single differential amplifier having emitter coupled transistors are coupled to the feedback loop and to the data ports and is responsive to control signals to selectively cause either the feedback loop to latch data or a selected one of the data ports to transmit data. The control signals are derived from a single clock signal, its inversion and a select signal. A nonoverlap region is created by raising the voltage range of either the clock signal or its inversion so that A and B latches can be used.

Abstract: An output drive circuit for LSI and VLSI ECL chips is presented. The drive circuit converts the logic levels of the ECL chip to those required by an external circuit being driven. The driver circuit includes a differential amplifier (21) having a selectable switching threshold level. One output signal line from the differential amplifier is coupled to an emitter follower output transistor (Q10) having a resistor (R17) placed in series with an output node (26). An active pulldown transistor (Q11) is connected between the output node and a negative voltage reference level. The base terminal of the pulldown transistor is driven from a current source. A capacitor (C1) is connected between the base of the pulldown transistor and the other output signal line of the differential amplifier. A temperature compensation circuit (23) causes the output signal levels appearing on the output node to track the variations in signal levels of the external circuit caused by temperature changes.

Abstract: A current source circuit selectively supplying at least one regulated output current. A reset pulse is provided concurrently with current source inhibit. The current source is adapted to low voltage circuits and dissipates minimal power for all modes of operation.