Abstract: A circuit is provided for multiplexing data packets, each having sets of n digital words and a residual set of r digital words. The multiplexing arrangement includes an output terminal (OUT), input memory units (RAM0-RAM3) each to receive and to store the data packets in memory portions and each to store n digital words, and a multiplexer (MUX) coupled to the input memory units (RAM0-RAM3) and to transfer the data packets thereof to the output terminal (OUT). The circuit also includes a register (RGN) and a residual register (RGR), each connected in parallel to the input memory units (RAM0-RAM3). The register (RGN) reads and transfers the sets of n digital words to the multiplexer (MUX). The residual register (RGR) reads and transfers the residual set of r digital words to the multiplexer (MUX). The multiplexer (MUX) combines the set of n digital words and the residual set of r digital words, forming a combined set, and providing at least a portion of the combined set to the output terminal (OUT).

Abstract: A synchronizing circuit to synchronize a digital input signal (DIN) with a clock signal (CK1) includes a detection circuit (DC) which checks if a present (SA) sample of a clock signal (CK3) being synchronized with the digital input signal, is equal to the previous (SB) sample, both samples being taken at an interval equal to the period (T) of the clock signal synchronized with the output signal. When the samples differ, the detection circuit generates a phase adjustment signal (CLR), which triggers a phase adjustment circuit (PAC) to ensure a return to synchronism by phase shifting the signal (ES) controlling the sampling of the digital input signal.

Abstract: The semiconductor device and arrangement include a thyristor switch (T1-T3) with associated turn-on (DM) and turn-off (PM1, PM2) devices. The thy=ristor switch includes a PNP transistor (T1) and one or two NPN transistors (T2, T3) each of which has an emitter constituted by a path of separate regions (115) of N+ material each completely surrounded by P+ material of a zone (110). This path either has a boat shape and partly surrounds and is located at a constant distance of a substantially rectangular zone (109) of P+ material constituting the emitter of the PNP transistor (T1), or has an S-shape and is located at a constant distance of the S-shaped emitter of the PNP transistor (T1).