Abstract: A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit.

Abstract: An apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device includes at least two main memory arrays comprised of a plurality of memory cells aligned in rows and/or columns and a shared redundancy circuit. The redundancy circuits preferably include a plurality of redundancy rows and a redundancy decoder which is configured for accessing the redundancy rows whenever a read or write operation involves use of a defective row within the main memory arrays for which a redundant row has been substituted. Preferably, each main memory array has access to the shared redundancy circuit. The shared redundancy circuit is used for substituting defective rows within a corresponding main memory array. The shared redundancy circuit provides extra redundant capacity to both of the main memory arrays.

Abstract: An equalization and precharge circuit precharges and equalizes local input/output (LIO) signal lines between each memory access operation within a memory circuit. The equalization and precharge circuit includes a local voltage circuit which maintains the level of the LIO signal lines at a standby voltage level during standby periods. Preferably, the standby voltage level is approximately equal to half of the supply voltage VCC. Separate precharge and equalization circuits are included to precharge and equalize the LIO signal lines between memory access operations. During precharge periods, a precharge control signal LIOPC is preferably at a logical high voltage level for a predetermined period of time between memory access operations, thereby forming a fixed-width pulse and raising the LIO signals to a known precharge level. The LIO signal lines are charged to a known level equal to the standby voltage level plus a voltage V(t) during the precharge and equalization period.

Abstract: The secondary power supply Vbb which powers components on a semiconductor device receives power from a distributed primary power supply Vbb. During the power-up portion for the secondary power supply Vbb, a main driver amplifier 13 provides the power. After the secondary power supply Vbb has reached the desired voltage level, a standby driver amplifier 14 is used to maintain the desired voltage level. In the present invention, the main driver amplifier 13 is activated by a time base unit 21, 22 time in response activation of the primary power supply. The time base unit 21, 22 can simultaneously inactivate the standby driver amplifier 14, or the standby power supply can operate independently of the main driver amplifier 13. After a time interval sufficient to insure that the output from the secondary power supply has reached the desired voltage level, the main driver amplifier 13 is inactivated and the standby (i.e., lower power) amplifier provides the steady state power.

Abstract: The plate voltage for a Dynamic Random Access Memory storage cell array is provided by two amplifiers. The first amplifier operates at a relatively low power level and compensates for leakage in the storage cell array, the compensation initiated by a departure of the plate from a nominal value which exceeds a preselected amount. The second amplifier operates at a higher power level and provides compensation for transients in the plate voltage resulting from the charging and discharging of the storage cells. Because the transients occur when the storage cells are accessed, the second amplifier is enabled only when a group of storage cells is accessed. In addition to operating at a higher power level, the second amplifier is more sensitive and responds to smaller excursions from the nominal voltage. Both the first and the second amplifiers have separate driver circuits for responding to excursions above and for responding to excursions below the nominal voltage.

Abstract: The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, at least one transistor and a control circuit. One of source/drain of a first transistor (26) in the slew circuit is connected to Vss, the other of the source/drain of the first transistor (26) is connected to the substrate, or in another embodiment of the invention, to one of a source/drain of a second transistor (28), the gate and other of the source/drain of the second transistor (28) being connected to the substrate. A control circuit is connected to the gate of the first transistor for controlling the passage of voltage from the one of a source/drain of the first transistor (26) to the substrate via the gate and the one of a source/drain of the second transistor (28).

Abstract: The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, first and second transistors and a control circuit. One of a source/drain of the source/drain of the first transistor is connected to a reference voltage. One of a source/drain of the second transistor is connected to a gate of the first transistor, the other of the source/drain of the second transistor is coupled to receive a first voltage signal from a substrate pump. The control circuit is connected to the gate of the second transistor for controlling the passage of current from the other of the source/drain of the second transistor to the one of a source/drain of the second transistor.

Abstract: The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, at least one transistor and a control circuit. One of a source/drain of a first transistor in the slew circuit is connected to Vss, the other of the source/drain of the first transistor is connected to the gate and one of a source/drain of a second transistor, the other of the source/drain of the second transistor is connected to the substrate. A control circuit is connected to the gate of the first transistor for controlling the passage of voltage from the one of a source/drain of the first transistor to the substrate via the gate and the one of a source/drain of the second transistor. The sensitivity of the slew circuit can be made programmable by adding one or more more n-channel transistors in stacked diode configuration between the other of the source/drain of the first transistor and the substrate.

Abstract: A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit.