Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.

Abstract: A method for communicating with an input/output (I/O) adapter configured to communicate with a locally attached I/O device are provided using cached address translations. With the method, in response to receiving a storage transaction request, a queue element is created in a command queue specifying an untranslated buffer address. The queue element may be retrieved by the I/O adapter and a determination may be made as to whether the queue element contains a read operation command. If so, a translation request may be sent from the I/O adapter to a root complex at substantially a same time as the read operation command is sent to a locally attached external I/O device. The translated address corresponding to the untranslated address of the queue element may be returned and stored in the I/O adapter prior to receiving the data read from the external I/O device.