Abstract: The invention relates to a patella gripper for a patella, comprising a retaining element (3; 53) and a contact finger apparatus (4; 54), wherein the contact finger apparatus (4; 54) is arranged on the lower face of the retaining element (3; 53), wherein the contact finger apparatus (4; 54) comprises at least two contact finger units (4.1, 4.2; 54.1), which are arranged on opposite sides of the retaining element (3; 53), and wherein the contact finger apparatus (4; 54) is designed in such a way that the patella can be moved in the cranial-caudal direction and in the medial-lateral direction by means of the contact finger units (4.1, 4.2; 54.1). The invention further relates to a device (20; 60) having such a patella gripper (1; 51).

Abstract: The invention relates to a patella gripper for a patella, comprising a retaining element (3; 53) and a contact finger apparatus (4; 54), wherein the contact finger apparatus (4; 54) is arranged on the lower face of the retaining element (3; 53), wherein the contact finger apparatus (4; 54) comprises at least two contact finger units (4.1, 4.2; 54.1), which are arranged on opposite sides of the retaining element (3; 53), and wherein the contact finger apparatus (4; 54) is designed in such a way that the patella can be moved in the cranial-caudal direction and in the medial-lateral direction by means of the contact finger units (4.1, 4.2; 54.1). The invention further relates to a device (20; 60) having such a patella gripper (1; 51).

Abstract: The present invention discloses a system and method for preventing a computer from initiating new cycles after a user has requested a reboot of the computer. The invention includes a programmable logic device that monitors the reset request (SRESET) signal, and in response places the central processing unit (CPU) of the computer in a hold state. The programmable logic device does this by issuing a hold (HOLD) signal to the CPU and receives back from the CPU a hold acknowledge (HLDA) signal. After the HLDA signal is received, the programmable logic device issues a CPU reset (RESETCPU) signal, which causes the CPU to reset after a certain number of clock cycles have passed. By placing the CPU in a hold state, the programmable logic device prevents the CPU from initiating new cycles just prior to resetting, which could result in corruption of the computer system.