Patents by Inventor Daniel Fernandez Martinez

Daniel Fernandez Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10065855
    Abstract: An integrated circuit and the method to produce the integrated circuit comprising: a substrate (10); active devices (11); plurality of metal layers (17), wherein said metal layers are separated by dielectric layers (13) and connected to each other by plurality of vias (19); at least one micromechanical region (15) wherein some of the dielectric layers are removed leaving hollow spaces (23), thereby some of said metal and via layers form a micromechanical device in said micromechanical region, wherein said micromechanical device comprises at least one multi-layer structure (165) that is built of a plurality of metal layers and at least one via layer and said multi-layer structure is characterized by that at least two metal layers of said multi-layer structure are joined by at least one modified via (41).
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 4, 2018
    Assignees: UNIVERISTAT POLITECNICA DE CATALUNYA
    Inventors: Piotr Jozef Michalik, Daniel Fernández Martínez, Jordi Madrenas Boadas
  • Publication number: 20180148329
    Abstract: An integrated circuit and the method to produce the integrated circuit comprising: a substrate (10); active devices (11); plurality of metal layers (17), wherein said metal layers are separated by dielectric layers (13) and connected to each other by plurality of vias (19); at least one micromechanical region (15) wherein some of the dielectric layers are removed leaving hollow spaces (23), thereby some of said metal and via layers form a micromechanical device in said micromechanical region, wherein said micromechanical device comprises at least one multi-layer structure (165) that is built of a plurality of metal layers and at least one via layer and said multi-layer structure is characterised by that at least two metal layers of said multi-layer structure are joined by at least one modified via (41).
    Type: Application
    Filed: April 20, 2016
    Publication date: May 31, 2018
    Inventors: Piotr Jozef MICHALIK, Daniel FERNÁNDEZ MARTÍNEZ, Jordi MADRENAS BOADAS
  • Publication number: 20140225250
    Abstract: A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.
    Type: Application
    Filed: November 13, 2013
    Publication date: August 14, 2014
    Applicant: Baolab Microsystems SL
    Inventors: Josep Montanya Silvestre, Marco Antonio Llamas Morote, Daniel Fernandez Martinez, Juan José Valle Fraga, Albert Mola
  • Publication number: 20120090393
    Abstract: The systems and methods described herein address deficiencies in the prior art by enabling the fabrication and use of accelerometers, whether MEMS-based, NEMS-based, or CMOS-MEMS based, in the same integrated circuit die as a CMOS chip. In one embodiment, the accelerometer is fabricated on the same integrated circuit die as a CMOS chip using a typical CMOS manufacturing process.
    Type: Application
    Filed: June 20, 2011
    Publication date: April 19, 2012
    Applicant: Baolab Microsystems SL
    Inventors: Josep Montanya Silvestre, Daniel Fernandez Martinez