Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.

Abstract: In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.

Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.

Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.

Abstract: Systems and methods for virtually partitioning an integrated circuit includes identifying dimensional attributes of a target input dataset; selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on: the dimensional attributes of the target dataset, and architectural attributes of an integrated circuit; disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme; identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset; virtually partitioning the architecture of the integrated circuit into a plurality of distinct partitions of processing cores of the integrated circuit; and mapping each of the plurality of distinct subsets of data to one of the plurality of distinct partitions of processing cores of the integ

Abstract: In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.

Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

Abstract: In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.

Abstract: Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.

Abstract: Systems and methods for virtually partitioning an integrated circuit may include identifying dimensional attributes of a target input dataset and selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on the dimensional attributes of the target dataset and architectural attributes of an integrated circuit. The method may include disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme and identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset.

Abstract: A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.

Abstract: Systems and methods for accessing remote digital services by using embedded circuitry included in an electronic device.

Abstract: Devices and circuitry for computing hash values.

Abstract: A first device may be coupled to a second device over a network. The first device may maintain a first cryptocurrency wallet and may include mining circuitry that generates cryptocurrency rewards for the wallet. The first device may transmit a communications request to the second device. The second device may transmit payment information identifying a second wallet and a selected authentication amount to the first device. The second device may select the authentication amount to perform a desired amount of device connection rate limiting. The first device may generate an authentication transaction for a cryptocurrency network to transfer the authentication amount from the first wallet to the second wallet. The second device may determine whether the authentication transaction has been verified by the cryptocurrency network. In response to determining that the authentication transaction has been verified by the cryptocurrency network, the second device may establish the communication link.

Abstract: Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.

Abstract: A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.

Abstract: Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.

Abstract: Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.

Abstract: Systems and methods for virtually partitioning an integrated circuit includes identifying dimensional attributes of a target input dataset; selecting a data partitioning scheme from a plurality of distinct data partitioning schemes for the target input dataset based on: the dimensional attributes of the target dataset, and architectural attributes of an integrated circuit; disintegrating the target dataset into a plurality of distinct subsets of data based on the selected data partitioning scheme; identifying a virtual processing core partitioning scheme from a plurality of distinct processing core partitioning schemes for an architecture of the integrated circuit based on the disintegration of the target input dataset; virtually partitioning the architecture of the integrated circuit into a plurality of distinct partitions of processing cores of the integrated circuit; and mapping each of the plurality of distinct subsets of data to one of the plurality of distinct partitions of processing cores of the integ