Abstract: Implementations described herein generally relate to polishing articles and methods of manufacturing polishing articles used in polishing processes and cleaning processes. More particularly, implementations disclosed herein relate to composite polishing articles having graded properties. In one implementation, a polishing article is provided. The polishing article comprises one or more exposed first regions formed from a first material and having a first zeta potential and one or more second exposed regions formed from a second material and having a second zeta potential, wherein the first zeta potential is different from the second zeta potential.

Abstract: Embodiments of the present disclosure relate to advanced polishing pads with tunable chemical, material and structural properties, and methods of manufacturing the same. According to one or more embodiments, a method for forming or otherwise preparing a polishing article by sequentially forming a plurality of polymer layers is provided and includes: (a) dispensing a plurality of droplets of a polymer precursor composition onto a surface of a previously formed at least partially cured polymer layer, where the polymer precursor composition contains a first precursor component containing an epoxide group and a photoinitiator component which generates a photoacid when exposed to UV light, (b) at least partially curing the plurality of droplets to form an at least partially cured polymer layer, and (c) repeating (a) and (b).

Abstract: Embodiments include methods for a user equipment (UE) configured to operate in a radio access network (RAN). Such methods include receiving, from a radio node in the RAN, a new feedback indicator (NFI) that indicates whether acknowledgement signaling previously scheduled for transmission by the UE was received by the radio node. The acknowledgement signaling is associated with one or more first downlink (DL) hybrid ARQ (HARQ) processes. Such methods include, when the NFI indicates the acknowledgement signaling was not received by the RAN node, selecting a first HARQ codebook to be used for encoding the acknowledgement signaling together with further acknowledgement signaling associated with one or more second DL HARQ processes. Such methods include, using the selected first HARQ codebook, encoding the acknowledgement signaling and the further acknowledgement signaling to obtain first encoded information and transmitting the first encoded information to the radio node via an uplink (UL) channel.

Abstract: A syringe stabilizing apparatus has a base and a syringe support. The syringe support is vertically disposed above the base, elevating a fluid-filled portion of an infusion set vertically above the base and orienting a delivery end of the fluid-filled portion upwardly relative to a horizontal plane to take advantage of a gravitational effect on a fluid during delivery of the fluid from the fluid-filled portion to a patient. The syringe support comprises a first retainer and a selectively actuated tube clamp. The first retainer has an opening in which a rigid portion of the infusion set is received and retained therein without further user intervention. The selectively actuated tube clamp is operatively aligned with the first retainer. A flexible tube extending from the rigid portion of the infusion set extends through the selectively actuated tube clamp.

Abstract: A system and method for determining a Physical Uplink Control Channel (PUCCH) power control parameter h(nCQI,nHARQ) for two Carrier Aggregated (CA) PUCCH formats—PUCCH format 3 and channel selection. The value of h(nCQI,nHARQ) may be based on only a linear function of nHARQ for both of the CA PUCCH formats. Based on the CA PUCCH format configured for the User Equipment (UE), the e-Node B (eNB) may instruct the UE to select or apply a specific linear function of nHARQ as a value for the power control parameter h(nCQI,nHARQ), so as to enable the UE to more accurately establish transmit power of its PUCCH signal. Values for another PUCCH power control parameter—?F_PUCCH(F)—are also provided for use with PUCCH format 3. A new offset parameter may be signaled for each PUCCH format that has transmit diversity configured.

Abstract: According to some embodiments, a method in a network node comprises determining a first uplink/downlink scheduling pattern for a first plurality of consecutive subframes; transmitting the first uplink/downlink scheduling pattern to a wireless device; transmitting at least one subframe to the wireless device according to the first uplink/downlink scheduling pattern; determining a second uplink/downlink scheduling pattern for a second plurality of consecutive subframes, wherein the first plurality of consecutive subframes and the second plurality of consecutive subframes share at least one subframe; and transmitting the second uplink/downlink scheduling pattern to the wireless device.

Abstract: An electronic device includes a housing defining an internal volume, a front opening, and a rear opening. The electronic device can include a display component disposed at the front opening and a rear cover disposed at the rear opening. A logic board can be disposed in the internal volume. The device can also include a thin film thermopile including a cold junction bonded to the logic board and a hot junction bonded to the rear cover.

Abstract: A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.

Abstract: System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.

Abstract: Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.

Abstract: With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an “OFF” state before the burning and an “ON” state with a stable low-resistance path after the burning.

Abstract: Alternate routing tables selected according to data packet priority or according to source and destination addresses of data packet. Data packet propagated to egress port according to indicator provided by selected routing table with expediency dictated by data packet priority or priority indicator stored in the selected routing table.

Abstract: A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.

Abstract: Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.

Abstract: System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle.

Abstract: Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle.