Abstract: A device and method for generating a representation of a subject's attention level. The device measures brain signals from the subject; extracts temporal features from the brain signals; classifies the extracted temporal features using a classifier to give a score X1; extracts spectral-spatial features from the brain signals; selects spectral-spatial features containing discriminative information between concentration and non-concentration states from the set of extracted spectral-spatial features; classifies the selected spectral-spatial features using a classifier to give a score X2; combines the scores X1 and X2 to give a single score; and presents the score to the subject.

Abstract: According to one aspect, there is provided a method for assessing the treatment of attention-deficit/hyperactivity disorder (ADHD) in a subject, the method comprising: obtaining electroencephalographic (EEG) data relating to a plurality of subjects diagnosed with ADHD; extracting, for each of the plurality of subjects, at least one feature from the EEG data relating to that subject; formulating a prediction model by performing regression analysis to map the extracted features against one or more markers for each of the plurality of subjects; and determining that the prediction model provides an ADHD assessment if one or more of the markers are indicators of a clinical measure of interest.

Abstract: Systems and methods are described herein that reduce the read latency of a cache by separating read and write column select signals that cause the cache to initiate certain read and write operations, respectively.

Abstract: Systems and methods are described herein that reduce the read latency of a cache by separating read and write column select signals that cause the cache to initiate certain read and write operations, respectively.

Abstract: A device and method for generating a representation of a subject's attention level. The device comprises means for measuring brain signals from the subject; means for extracting temporal features from the brain signals; means for classifying the extracted temporal features using a classifier to give a score x1; means for extracting spectral-spatial features from the brain signals; means for selecting spectral-spatial features containing discriminative information between concentration and non-concentration states from the set of extracted spectral-spatial features; means for classifying the selected spectral-spatial features using a classifier to give a score x2; means for combining the scores x1 and x2 to give a single score; and means for presenting said score to the subject.

Abstract: A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

Abstract: An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.

Abstract: An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

Abstract: A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

Abstract: A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

Abstract: An approach to selectively powering a memory device is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various methods are provided to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

Abstract: A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

Abstract: An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.

Abstract: An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

Abstract: A system, method and related software architecture are disclosed as a platform for developing and deploying RFID-enabled software applications. The platform is a framework between these applications and their connected physical RFID devices. The runtime version of this platform can be thought of as a logical RFID device. The platform allows RFID-enabled applications securely communicate with physical RFID devices to monitor their status and to access their tag data. The platform includes externalized APIs for accessing tag data, an event manager to alert applications of events coming from RFID devices and tags, data manager to filter and reconcile data returned from physical RFID readers before relaying them to applications, device manager to monitor the RFID device status for network management, and secured communication channels with data encryption.

Abstract: A system, method and related software architecture are disclosed as a platform for developing and deploying RFID-enabled software applications. The platform is a framework between these applications and their connected physical RFID devices. The runtime version of this platform can be thought of as a logical RFID device. The platform allows RFID-enabled applications securely communicate with physical RFID devices to monitor their status and to access their tag data. The platform includes externalized APIs for accessing tag data, an event manager to alert applications of events coming from RFID devices and tags, data manager to filter and reconcile data returned from physical RFID readers before relaying them to applications, device manager to monitor the RFID device status for network management, and secured communication channels with data encryption.

Abstract: A method, system and computer readable medium for managing a user online financial transaction at a destination ecommerce web site using a credit or debit card account of the user, including a) transmitting an activation command to a financial institution processing financial transactions for activating the credit or debit card account of the user; b) submitting a charge request for the credit or debit card account to the financial institution via a destination e-commerce web site to which the user is logged in while the credit or debit card account is in the activated status; and c) transmitting a de-activation command to said financial institution for de-activating the credit or debit card account, wherein the financial institution only accepts and processes charge requests received from e-commerce web sites while the credit or debit card account is in the activated status and wherein the financial institution declines charge requests while said credit or debit card account is in the de-activated status, an