Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: Solvent-free UV-curable polymer materials derived from miscible blends of reactive organic monomeric, oligomeric and low molecular polymeric systems and organic and inorganic fillers such as polytetrafluoroethylene and talc are provided to form polymer-filler composite compositions for use in the fabrication and repair of electronic components and microelectronic assembly processes. The composition contains a preformed thermoplastic or elastomeric polymer/oligomer with reactive end groups, a monofunctional and/or bifunctional acrylate monomer, a multifunctional (more than two reactive groups) acrylated/methacrylated monomer, a photoinitiator and a fluorocarbon polymer powder as an organic filler which is preferably PTFE and an inorganic filler such as talc. A nano-filler may also be used as the inorganic filler alone or in combination with another inorganic filler such as talc.

Abstract: A manifold apparatus, system and method for thermally controlling a substrate whereby a manifold body having a microjet array and a drain array traversing there-through in a direction orthogonal to a substrate surface and parallel to each other is attached to the substrate surface for heating or cooling thereof. A cavity of the manifold body resides over the substrate surface such that liquid is emitted from the liquid microjets into the cavity for contact with the substrate surface, while the drains orthogonally remove spent liquid from the cavity. The manifold body is designed and configured into a plurality of cooling cells, whereby each cooling cell has a liquid microjet surrounded by at least three drains for preventing interactions between adjacent liquid microjets within adjacent cooling cells. Gas microjets may also traverse through the manifold body to form an atomized liquid spray for contact with the substrate surface.

Abstract: A method and apparatus are provided for reworking of finishing metallurgy on pads of electronic components. The pads are copper or copper/nickel and have a layer of nickel thereon and an overlying layer of gold. The gold layer is removed first followed by the nickel layer and then the component is treated to remove etch and corrosion products. Media blasting is then used to restore the pads to their original condition as on prime parts. The pads are then replated using conventional nickel and gold plating solutions to form the reworked component.

Abstract: A method and apparatus are provided for reworking of finishing metallurgy on pads of electronic components. The pads are copper or copper/nickel and have a layer of nickel thereon and an overlying layer of gold. The gold layer is removed first followed by the nickel layer and then the component is treated to remove etch and corrosion products. Media blasting is then used to restore the pads to their original condition as on prime parts. The pads are then replated using conventional nickel and gold plating solutions to form the reworked component.

Abstract: A self scrubbing buckling beam contactor for contacting an array of pads positioned on a device under test is described. The contactor consists of three insulating dies: a top, an offset and a lower die separated from each other by an insulated spacer of variable thickness. Each die is provided with holes. The buckling beam has an array of flexible wires positioned substantially perpendicular to the dies, each of the flexible wires crossing a corresponding hole in each of the top, offset and lower dies to allow each wire respectively contact a pad of the device under test. By shifting the center of the hole of the lower die relative to the center of the offset die, the tip of the wire exits from the lower die at an angle with respect to the plane formed by the pads of the device under test.

Abstract: A stripping composition and a method of using the stripping composition to remove cured resins such as elastomeric silicone adhesive deposits from ceramic and metal surfaces of electronic modules to provide reworkability options in assembly processes including diagnostic parts, parts replacement and recovery of substrates from test vehicles is provided. The stripping compositions comprise a base preferably an organic base such as a quaternary ammonium hydroxide, a surfactant and a high boiling environmentally and chemically safe solvent such as di- or tri-propylene glycol alkyl ether. In another stripping composition, the base is used in combination with a mixture of N-alkyl pyrrolidone components, preferably an N-alkyl pyrrolidone and a N-cycloalkyl pyrrolidone. The stripping compositions are used to contact an electronic module having a cured resin such as a silicone adhesive residue deposit on the module surface to dissolve, remove or strip the deposit.

Abstract: The present invention relates to an improved process for forming negative tone images of photosensitive polyimides on a substrate having improved wall angles.

Abstract: Standard processing techniques for creating a patterned polyimide film from a radiation sensitive polyimide film forming composition are modified to include a post-develop, flood exposure/hardening step which crosslinks precursors of the polyimide film prior to curing. The flood exposure/hardening step prevents pull-back of the wall profile which occurs during the shrinkage of radiation sensitive polyimide film forming composition which occurs during thermal curing.

Abstract: In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.