Abstract: A method for reducing noise in a four-quadrant multiplier having first and second cross-coupled pairs of differential bipolar transistors, differential input current terminals connected with a first pair of common junctions of the respective pairs of differential transistors and the differential output current terminals cross coupled to form a second pair of common junctions of the respective pairs of differential transistors is described. The method includes providing a noise current path from the differential input current terminals to a bias voltage, the noise current path substantially bypassing the differential output current terminals when the gain of the multiplier is near zero.

Abstract: An integrated circuit includes a termination for a transmission line having a predetermined characteristic impedance. The termination includes a controllable impedance circuit, including a multiplier, coupled to the transmission line. A reference impedance, placed external to the integrated circuit, has an impedance related to the characteristic impedance of the transmission line.

Abstract: A jitter measurement method using a down-mixing or down-converting topology in a jitter measurement system preserves the jitter UI rather than the jitter seconds. An input serial data stream at a high baud, after conversion from NRZ to RZ if necessary, is mixed with a stable local oscillator frequency that is close to that of the high baud. The difference between the high baud and the local oscillator frequency is passed by a filter to a clock recovery circuit, to an amplitude modulation removal stage or to a digitizer as a lower rate serial stream. The clock recovery circuit recovers a lower rate clock from the lower rate serial stream upon which the jitter measurement is performed by a jitter measurement stage. The amplitude modulation removal stage converts the lower rate serial stream to a lower rate NRZ signal upon which the jitter measurement is performed directly by the jitter measurement stage or via the clock recover circuit.

Abstract: A method for reducing noise in a four-quadrant multiplier having first and second cross-coupled pairs of differential bipolar transistors, differential input current terminals connected with a first pair of common junctions of the respective pairs of differential transistors and the differential output current terminals cross coupled to form a second pair of common junctions of the respective pairs of differential transistors is described. The method includes providing a noise current path from the differential input current terminals to a bias voltage, the noise current path substantially bypassing the differential output current terminals when the gain of the multiplier is near zero.

Abstract: A method for generating an in-phase (I) output signal and a quadrature-phase (Q) output signal from an input signal reduces phase error in the I/Q generator by delaying-and-doubling an input signal to produce a Q output signal and delaying the input signal twice and subtracting the same from the input signal to produce an I output signal. The I/Q generator includes a first 90°-phase delay circuit receiving an input signal and outputting an intermediate Q signal; a second 90°-phase delay circuit receiving the intermediate Q signal and producing an intermediate I signal. It also includes a signal doubler receiving the intermediate Q signal and producing a Q output signal of twice the amplitude of the input signal at a 90° phase angle. Finally, the generator includes a signal differencer receiving the input signal and the intermediate I signal and producing an I output signal of substantially twice the amplitude of the input signal at a 0° phase angle.

Abstract: A digital phase synthesizer includes a source of successive phase data signals. An interpolator generates successive edge placement data signals in response to each of the successive phase data signals. A phase modulator generates an output clock signal having edges placed at times determined by the successive edge placement data signals. Similarly, a digital phase analyzer includes a source of an serial binary input signal having edges. A phase demodulator generates successive data signals representing the location of each edge of the serial binary input signal. A decimator generates phase data signals at a lower rate than the edges of the serial binary input signal.

Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system 200 takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.

Abstract: A phase modulator circuit and method for generating an output signal having individually positionable edges is described. The phase modulator includes a programmable pulse generator, such as an interval counter, a delay, or a ring oscillator for producing the output signal, and a control value source, such as a memory, for delivering a sequence of control values to the generator. The control values determine the time between successive output pulses. A programmable interval counter includes a free running counter, the output of which is compared to a control value, preferably stored as a modulo data value, to generate an output pulse. A first programmable delay circuit includes a ring oscillator having plural delay lines for fine control of edge positioning. To fully synchronize the delay circuit to a coarse control interval counter, the clock input to the interval counter can be provided by the ring oscillator.

Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system (200) takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.

Abstract: A first subset of components of a first set of pairs of complementary differential electrical signals representative of a numerical value expressed in a multi-bit thermometer code, is processed in accordance with a first set of Boolean functions to produce a first set of output electrical signal components , and a second subset of components of the first set of pairs of complementary differential electrical signals is processed in accordance with a second set of Boolean functions to produce a second set of output electrical signal components. The first and second subsets and the first and second sets of Boolean functions are such that the first and second sets of output electrical signal components when combined form a second set of pairs of complementary differential electrical signals representative of the same numerical value expressed in a second multi-bit code with fewer bits than the multi-bit thermometer code.

Abstract: A method and circuit for conditioning a received analog signal for input to an analog-to-digital converter circuit ("ADC"). For each clock period in which a conversion is triggered, a first analog value is provided during a first predetermined period and a second analog value is provided during a second predetermined period. The first analog value is representative of the received analog signal's instantaneous value at the moment selected for conversion. The second analog value is predetermined, typically being a null value. The signal conditioning circuit includes a hold circuit to hold the received analog signal's instantaneous value; a generating circuit that generates the second analog value; and an output circuit that selectively outputs the instantaneous value or the predetermined value to the ADC.

Abstract: Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.

Abstract: A transistor amplifier having a main amplifier exhibiting a substantially doubled f.sub.T characteristic and having error cancellation circuitry, wherein the standing current of the error cancellation circuitry is reused in powering the main amplifier. The main amplifier comprises an outer differential pair of transistors and an inner differential pair of transistors, each differential pair having an inverting side and a non-inverting side. The collectors of the transistors of the non-inverting side of the differential pairs are connected, respectively, at a first current summing node. The collectors of the transistors of the inverting side of the differential pairs are connected, respectively, at a second current summing node. The f.sub.

Abstract: A thermometer-to-binary encoder includes a set of J input stage encoders E(1) through E(J) and an output encoder D, where J= 2.sup.K is an integer greater than 1. A set of digital input signals each representing a separate bit of a thermometer code T is grouped into J signal subsets representing further thermometer codes T(1) through T(J) providing inputs to a set of input stage encoders E(1) through E(J) respectively. Encoder E(J) produces an N-K+1 bit output binary code B(J) representing thermometer code T(J). Encoders E(1) through E(J-1) produce M-bit output binary codes G(1) through G(J-1), respectively, comprising the lower M bits of a binary code representing thermometer codes T(1) through T(J-1), respectively, where M is an integer greater than 1. Output encoder D processes codes G(1) through G(J-1) and B(J) to produce a set of digital output signals representing a binary code Y representing input thermometer code T.

Abstract: An electrical circuit (30) corrects for the presence of noise current and current drift in the currents developed by each current source transistor Q.sub.0, Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.n in a current source array. The electrical circuit corrects for the presence of noise current and current drift by simultaneously inducing in each current source correction currents whose values sum to cancel the current drift and noise. A noise suppression circuit includes an amplifier having an open loop gain, A.sub.v, which is configured to adjust the magnitudes of the multiple currents in response to the introduction of a noise current, i.sub..delta., in any one of the currents. The adjustment substantially cancels i.sub..delta. and thereby substantially reduces the presence of i.sub..delta. in the output current. The presence of i.sub..delta. in the output signal is substantially equal to i.sub..delta. /(1+A.sub.v).

Abstract: The present invention constitutes a memory system comprising a multiple number of individual memory units (40-47) for storing digital data from a variable number of data input streams and for efficiently using the memory capacities of the memory units in the system by controlling the routing of data between the memory units. Each one of the memory units includes a set of input multiplexers (100-103), a set of shift/shadow registers (110-113) and a memory component (120) having a RAM memory array (121). The components of the memory units are implemented on a single integrated circuit chip. The input multiplexers allow alternate data streams to be selected for input to the shift/shadow registers. The shift/shadow registers are operative for enabling data to be transferred to and from the memory array at speeds slower than the rate at which these data are received by the system.

Abstract: An improved shift register uses fewer than 2*N latches, where N is the capacity in bits of the shift register and also the propagation delay from the input to the output of the shift register in terms of the system clock. An m-phase set of clocks are used, where m is an even number larger than two and and the duration of each clock phase is one half of the period of the system clock. The latches are arranged in m/2 strings of length 2N/(m-1), instead of one long string. The strings of latches are offset with respect to each other by two phases in terms of their connection to the multiphase clock, with each successive latch in each string being enabled by the clock signal whose phase immediatedly precedes the phase of the clock signal used to enable the preceding latch in that string. A multiplexer at the output puts the data from the multiple strings of latches back into one serial output stream.

Abstract: A state element having a pair of parallel-connected, inversely-enabled latches forms the basic state-machine building block. A flip-latch is formed by combining this basic element with a multiplexer for selectively outputting alternate outputs of the latches. A litch-latch is formed by using the basic element alone with the two inputs fed from one of a pair of identical logic elements and feeding back the output from each latch to the logic element from which the input is not received. Other outputs of the logic elements are input into a multiplexer for alternately selecting the outputs from the respective logic elements to be the state machine output. These state elements function similarly to a flip-flop but generally produce less propagation delay and require a lower clocking signal frequency for a given state frequency.

Abstract: A method and an apparatus detect the presence of and correct for timing misalignment between waveforms acquired by digital oscilloscopes. In a preferred embodiment, a digital oscilloscope (50) includes a waveform alignment system (60) that receives a first waveform (86) and a similar second waveform (88) of a periodic electrical signal. A digital signal processor (80) of the waveform alignment system generates an autocorrelation value in connection with the first waveform and a first cross-correlation value in connection with the first and second waveforms and compares the values to determine whether they differ by more than a preselected tolerance, thereby to detect a timing misalignment between the first and second waveforms.

Abstract: An encoder circuit converts a thermometer code into an equivalent adjacent binary code wherein only a single bit is changed to minimally increment or decrement the value of the binary code. The encoder logic is grouped so that the state of any single bit of the thermometer code can affect the state of one and only one bit of the binary code whereby when any least significant thermometer code bit is at an invalid logic level, the invalid level is propagated through the encoder circuit to only a single, least significant binary code bit, without the introduction of any logical errors. The invalid binary code bit is then stabilized to a valid level by one or more latches.