Abstract: One embodiment of the invention includes an apparatus, such as a bridge, for use in connection a with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA).

Abstract: One embodiment of the invention includes an apparatus, such as a bridge, for use in connection with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest priority interrupt destination arbitration (LPIDA). The apparatus also includes lowest priority logic to perform the LPIDA to select processor in the computer system is to receive an interrupt message based on contents of the remote priority capture logic. Another embodiment of the invention includes a multi-processor system having processors and a processor bus coupled to the processors. The system includes remote priority capture logic to hold task priority data indicative of a task priority of the processors while they are available for lowest priority interrupt destination arbitration (LPIDA).

Abstract: An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Abstract: In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto.

Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Abstract: An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.