Patents by Inventor Daniel G. OUELLETTE
Daniel G. OUELLETTE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12051698Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.Type: GrantFiled: September 23, 2020Date of Patent: July 30, 2024Assignee: Intel CorporationInventors: Daniel G. Ouellette, Daniel B. O'Brien, Jeffrey S. Leib, Orb Acton, Lukas Baumgartel, Dan S. Lavric, Dax M. Crum, Oleg Golonzka, Tahir Ghani
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Patent number: 11616192Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.Type: GrantFiled: June 29, 2018Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Tofizur Rahman, Christopher J. Wiegand, Justin S. Brockman, Daniel G. Ouellette, Angeline K. Smith, Andrew Smith, Pedro A. Quintero, Juan G. Alzate-Vinasco, Oleg Golonzka
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Publication number: 20220415890Abstract: Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Mohammad HASAN, Biswajeet GUHA, Oleg GOLONZKA, Leonard P. GULER, Leah SHOER, Daniel G. OUELLETTE, Pedro FRANCO NAVARRO, Tahir GHANI
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Patent number: 11489112Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.Type: GrantFiled: September 28, 2017Date of Patent: November 1, 2022Assignee: INTEL CORPORATIONInventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
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Patent number: 11404630Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.Type: GrantFiled: December 30, 2016Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Md Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Justin S. Brockman, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
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Publication number: 20220093597Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Daniel G. OUELLETTE, Daniel B. O'BRIEN, Jeffrey S. LEIB, Orb ACTON, Lukas BAUMGARTEL, Dan S. LAVRIC, Dax M. CRUM, Oleg GOLONZKA, Tahir GHANI
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Patent number: 11031545Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.Type: GrantFiled: September 30, 2016Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz
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Patent number: 10868233Abstract: Strain engineering of perpendicular magnetic tunnel junctions (PMTJs) is described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer.Type: GrantFiled: March 30, 2016Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz, Oleg Golonzka, Justin S. Brockman, Kevin P. O'Brien, Brian S. Doyle, Kaan Oguz, Tahir Ghani, Mark L. Doczy
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Patent number: 10804460Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.Type: GrantFiled: July 1, 2016Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Daniel B. Bergstrom, Justin S. Brockman, Oleg Golonzka, Tahir Ghani
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Patent number: 10770651Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.Type: GrantFiled: December 30, 2016Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
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Publication number: 20200203602Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.Type: ApplicationFiled: September 28, 2017Publication date: June 25, 2020Applicant: INTEL CORPORATIONInventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
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Publication number: 20200006635Abstract: A memory device includes a perpendicular magnetic tunnel junction (pMTJ) stack, between a bottom electrode and a top electrode. In an embodiment, the pMTJ includes a fixed magnet, a tunnel barrier above the fixed magnet and a free magnet structure on the tunnel barrier. The free magnet structure includes a first free magnet on the tunnel barrier and a second free magnet above the first free magnet, wherein at least a portion of the free magnet proximal to an interface with the free magnet includes a transition metal. The free magnet structure having a transition metal between the first and the second free magnets advantageously improves the switching efficiency of the MTJ, while maintaining a thermal stability of at least 50 kT.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Applicant: Intel CorporationInventors: Tofizur Rahman, Christopher J. Wiegand, Justin S. Brockman, Daniel G. Ouellette, Angeline K. Smith, Andrew Smith, Pedro A. Quintero, Juan G. Alzate-Vinasco, Oleg Golonzka
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Publication number: 20190378972Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.Type: ApplicationFiled: December 30, 2016Publication date: December 12, 2019Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
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Publication number: 20190334079Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.Type: ApplicationFiled: December 30, 2016Publication date: October 31, 2019Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Justin S. BROCKMAN, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
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Publication number: 20190221734Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.Type: ApplicationFiled: September 30, 2016Publication date: July 18, 2019Applicant: INTEL CORPORATIONInventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, MD Tofizur Rahman, Brian Maertz
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Publication number: 20190140166Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.Type: ApplicationFiled: July 1, 2016Publication date: May 9, 2019Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Brian MAERTZ, Daniel G. OUELLETTE, Kevin P. O'BRIEN, Kaan OGUZ, Brian S. DOYLE, Mark L. DOCZY, Daniel B. BERGSTROM, Justin S. BROCKMAN, Oleg GOLONZKA, Tahir GHANI
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Publication number: 20190027679Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.Type: ApplicationFiled: March 30, 2016Publication date: January 24, 2019Applicant: Intel CorporationInventors: Daniel G. OUELLETTE, Christopher J. WIEGAND, MD Tofizur RAHMAN, Brian MAERTZ, Oleg GOLONZKA, Justin S. BROCKMAN, Kevin P. O'BRIEN, Brian S. DOYLE, Kaan OGUZ, Tahir GHANI, Mark L. DOCZY