Patents by Inventor Daniel G. Young

Daniel G. Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8108731
    Abstract: A method of validating a configuration of a computer clusters includes transmitting a first neighbor identification to a first flexible service processor (FSP) arranged in the first computer cluster and a second neighbor identification to a second FSP arranged in the second computer cluster, connecting a first end of a cable to a first transceiver arranged in the first cluster and connecting a second end of the cable to a second transceiver arranged in the second cluster. The first neighbor identification is passed from the first transceiver to the second computer cluster and the second neighbor identification is passed from the second transceiver toward the first computer cluster. The first neighbor identification is compared with a desired first neighbor identification to establish a first comparison result, and the second neighbor identification is compared with a desired second neighbor identification to establish a second comparison result and a notice is generated.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Aruna V. Ramanan, Edward J. Seminaro, Alison B. White, Daniel G. Young
  • Patent number: 8020050
    Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Aruna V. Ramanan, Edward J. Seminaro, Alison B. White, Daniel G. Young
  • Patent number: 7940878
    Abstract: A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Baumgartner, Timothy C. Buchholtz, Andrew D. Davies, Thomas W. Liang, Andrew B. Maki, Thomas Pham, Dana M. Woeste, Daniel G. Young
  • Publication number: 20100275064
    Abstract: A method of validating a configuration of a computer clusters includes transmitting a first neighbor identification to a first flexible service processor (FSP) arranged in the first computer cluster and a second neighbor identification to a second FSP arranged in the second computer cluster, connecting a first end of a cable to a first transceiver arranged in the first cluster and connecting a second end of the cable to a second transceiver arranged in the second cluster. The first neighbor identification is passed from the first transceiver to the second computer cluster and the second neighbor identification is passed from the second transceiver toward the first computer cluster. The first neighbor identification is compared with a desired first neighbor identification to establish a first comparison result, and the second neighbor identification is compared with a desired second neighbor identification to establish a second comparison result and a notice is generated.
    Type: Application
    Filed: April 23, 2009
    Publication date: October 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Casimer M. DeCusatis, Aruna V. Ramanan, Edward J. Seminaro, Alison B. White, Daniel G. Young
  • Publication number: 20100275071
    Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.
    Type: Application
    Filed: April 23, 2009
    Publication date: October 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Casimer M. DeCusatis, Aruna V. Ramanan, Edward J. Seminaro, Alison B. White, Daniel G. Young
  • Patent number: 7573937
    Abstract: Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degree rotation). Each operational phase rotator should respond with an equal but opposite phase shift in order to maintain phase lock. Thus, after sweeping, each tap weight is exercised, which may help ensure defective tap weights in any (e.g., quadrant) are detected during testing.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: August 11, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Baumgartner, Anthony R. Bonaccio, Timothy C. Buchholtz, Charles P. Geer, Daniel G. Young
  • Publication number: 20080205570
    Abstract: A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Inventors: Steven J. Baumgartner, Timothy C. Buchholtz, Andrew D. Davies, Thomas W. Liang, Andrew B. Maki, Thomas Pham, Dana M. Woeste, Daniel G. Young
  • Publication number: 20020121017
    Abstract: A method for fabricating lithium batteries comprising providing a P2O5 drying aid between an exterior surface of a cell laminate and an interior surface of a container in which the cell laminate is sealed. A cell laminate is first formed from a transition metal chalcogenide positive electrode and a carbonaceous negative electrode with an electrolyte-containing separator there between. The cell laminate is then sealed in a container together with the P2O5 drying aid such that P2O5 is available during battery operation to react with moisture generated during charging and discharging of the battery cell.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 5, 2002
    Inventors: William J. Labarge, Daniel G. Young
  • Publication number: 20020122973
    Abstract: A method for preparing lithium-ion and lithium-ion polymer batteries to reduce water content and cell impedance. A battery having improved calendar life is prepared by electrochemically treating the activated cell by applying a voltage to the cell to react oxygen provided or trapped in the cell with moisture present as an unavoidable impurity. The electrochemical treatment of the present invention decreases the water content in the cell, thereby lowering cell impedance and extending battery life.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 5, 2002
    Applicant: DELPHI TECHNOLOGIES, INC.
    Inventors: Vesselin G. Manev, Daniel G. Young, Mohammad Parsian
  • Publication number: 20020122986
    Abstract: A lithium battery having a separator capable of storing excess lithium ions. As lithium ions are irreversibly adsorbed by the battery electrodes, they are replenished from the excess lithium stored in the separator material, thereby extending battery life. In an example of the present invention, molecular sieves, such as 13X molecular sieves, are used as the separator material. Molecular sieves are hydroscopic and therefore also react with moisture in the battery, thereby reducing cell impedance.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 5, 2002
    Inventors: William J. Labarge, Daniel G. Young
  • Patent number: 5530808
    Abstract: The present invention provides a method in a data processing system for efficiently sending a data packet from a source node to a destination node. The data processing system includes a multi-segment network having at least two segments, wherein the source node and the destination node are located within in different segments. Communication of a data packet from one segment to another segment is provided by an agent node. The present invention generates a data packet at the source node within a first segment on the multi-segment network. The data packet includes a source address, a destination address, and data. The data packet is then transmitted within the first segment and the source node retains ownership of the data packet. Thereafter, the data packet is received within the first segment at an agent node. The data packet is examined to determine the destination address and then transmit it to the destination node within a second segment in the multi-segment network.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: June 25, 1996
    Assignee: International Business Machines Corporation
    Inventors: William A. Hammond, George W. Nation, Daniel G. Young
  • Patent number: 5093908
    Abstract: A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.
    Type: Grant
    Filed: April 17, 1989
    Date of Patent: March 3, 1992
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Beacom, Jeffrey D. Brown, Mark R. Funk, Scott A. Hilker, Daniel G. Young